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基于VHDL的DDS程序。仅存储了四分之一周期的数据，优化的DDS。-VHDL-based DDS program. Only a quarter cycle of data storage, optimization of DDS.
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Verilog HDL语言编写的uart程序，在别人基础上改动和优化完成，quartus ii 10.0编译通过，可综合，板上仿真通过。将PC机发送的字符串发送回，可一次发送多个字符串。-Verilog HDL language uart program, in others on the basis of changes and optimization is complete, quartus ii 10.0 compiler, integrated, on-board through si
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Contains two clients receive link-level communications program, Based on wavelet transform digital watermarking algorithm matlab code, LCMV optimization design array signal processing.
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Minimum mean square error (MMSE) algorithm, LCMV optimization design array signal processing, Power System Transient Stability Program, can be transient stability.
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