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spi slave
- SPI 接口的VHDL和Verilog实现。slave模式
SPI_Slave
- SPI Slave example (VERILOG HDL)
VHD_Veri_spi
- 一个强大的符合SPI规范的VHDL/Verilog源码文件，传输模式和时钟相位均可以指定，采用同步时钟设计，可以工作在很高的频率下。支持主机及从机模式，强烈推荐使用！-A strong line with SPI standard VHDL/Verilog source files, transfer mode, and clock phase are to specify, using synchronous clock design can work in very high frequen
spi
- this the SPI slave module -this is the SPI slave module
spi_slave
- spi(serial peripheral interface) slave unit with Verilog-HDL
verilog-SPI-Controler
- 使用Verilog语言实现的SPI控制器，包括SPI主机和从机代码。-Using the Verilog language implementation of SPI controllers, including SPI master and slave codes.
spislave_latest.tar
- SPI接口的verilog代码，本代码是从机代码。-SPI interface verilog code, the code is slave machine code.
SPI_fpga_w_r_sigle
- verilog fpga spi slave 收发测试 有简单的协议 modelsim仿真通过 -simple protocol modelsim verilog fpga spi slave transceiver test simulation by
spi-verilog
- 用Verilog来实现SPI接口电路逻辑，实现主机与从处理器的通信-SPI interface circuit is implemented in Verilog logic between master and slave processor communication
spi
- spi slave verilog代码 spi slave verilog代码 spi slave verilog代码-spi slave verilog code spi slave verilog code spi slave verilog code
SPI-Verilog-123
- spi slave code s pi slave code spi slave code -spi slave code spi slave code spi slave code spi slave code
spi
- SPI 从机verilog设计,验证通过！-SPI interface slave verilog
V2.tar
- SDIO slave, written in verilog, does not support SPI mode.
Nitro-Parts-lib-SPI-master
- Nitro-Parts-lib-SPI Verilog SPI master and slave
spi master slave
- SPI master slave (fpga/verilog)
spi_8r8w
- 同时实现多个SPI从设备的连续读写，读写字节数可变化(implement multiply spi slave read/write operation, and the operation's bytes can be changed)