搜索资源列表
8251_8055_verilog
- 8251和8055的verilog源码，可进行综合和仿真，是学习SOC的好资料！-8251 and 8055 verilog the source, and integrated simulation, SOC is a good learning information!
AHBtoAPB.rar
- amba总线桥:ahb to asb!verilog hdl文档加代码，非常全，soc,amba bus bridge: ahb to asb! verilog hdl code for the document plus a very full, soc
mdio
- MDIO verilog RTL代码，SOC可以通过MDIO接口来访问外部PHY等慢速外设-MDIO verilog RTL code
Camera_Interface_Verilog
- 该源代码包是基于片上系统的摄像头接口的Verilog语言程序，它包括以下5部分：RTL源代码，测试平台，软件仿真C代码，FPGA综合时的sdc和ucf文件，说明文档。-This source code package is the camera interface module based on the SoC use Verilog language. It has the following 5 parts: RTL code, testbench, software simulating
ARM7_verilog
- arm 7 verilog code used setup soc
DW8051_ALL
- 包中包括, DW8051完整的Verilog HDL代码 两本手册: DesignWare Library DW8051 MacroCell, Datasheet DesignWare DW8051 MacroCell Databook 三篇51论文: 基于IP 核的PSTN 短消息终端SoC 软硬件协同设计 Embedded TCP/ IP Chip Based on DW8051 Core 以8051为核的SOC中的万年历的设计 -DW8051 is desi
mesh_dft
- 自己写一个关于维mesh结构的noc网络，verilog，仿真结果无误。-Write their own structure on the noc-dimensional mesh network, verilog, accurate simulation results.
soc-gr0040-010309
- xsoc vhdl verilog risc cpu soc implementation in very liitle cpld or fpga
lariviere2008uclinux
- xsoc vhdl verilog risc cpu soc implementation in very liitle cpld or fpga
I2C
- I2C主机端模块 具有avalon-MT总线接口 可挂载在Altera soc系统之上 使NiosII处理器具备I2C通信能力 模块由Verilog HDL编写 并经Cyclone II FPGA测试-I2C master modul which has a avalon-MT interface that can be attached to Altera SOC system. It provides NiosII I2C communication capability . This mo
soccccc
- 此文主要是基于VERILOG HDL 硬件实现的soc系统，主要功能是实现了基于Intel8051的滤波器系统-This article is based mainly on the soc VERILOG HDL hardware system, the main function is to achieve a filter system based on Intel8051
Timer
- 嵌入式系统的单片集成定时器的Verilog实现。可实现多种配置模式，可作为通用的定时器设计模板-This is a standed timer for an SOC design.It can realize multible function need to design an micro process circut
dynamic-voltage-scaling
- 用硬件描述语言编写的用于片上系统的低功耗的动态电压调节算法-Dynamic Voltage Scaling Algorithm designed in verilog Hard Descr iption Language using for low power of soc chips and some other pipelined design！
quick_reference
- SPECMAN LEARNING MATERIAL FOR VERIFICATION OF VHDL VERILOG SOC
or1200_sopc
- 用verilog语言编写的or1200+wishbone总线+串口uart+片上ram，最小系统soc。包括片上ram的软件系统（C语言编写）都有。但下载者要使用此系统需要很多工具链，搞soc的应该都装好了。 绝对原创！用quartusII11.0在Altera DE2-115上验证通过，Modelsim SE 6.5f仿真通过。-It s very strange for Chinese people communicating with each other in English. Ri
sockit_owm_latest.tar
- 1-wire master written in Verilog HDL, ready for integration into a FPGA or ASIC based SoC. A port of the 1-wire Public Domain Kit (version 3.10r2) from Maxim is also provided, with all the code required for integration into the Altera development
RC_Engine
- 用Verilog實現的推薦系統, 用於片上系統設計-It is the Verilog source code for recommendation system. It can be used in SoC design.
verilog
- vivado的led灯的学习程序，有兴趣学习soc的可以下载-the program for vivado study on SOC
Zet-1.3.1
- 在单片FPGA上实现九十年代初期PC，可安装Windows3.1及其他DOS系统。SOC中包含以80286(cpu),中断控制器,显示控制器(VGA),声音控制器,PS2(鼠标，键盘)等。是了解计算机历史变迁及学习SOC设计的重要资料！(ZET aims to implement an early 90`s PC on FPGA.Which include a 80286(cpu),interrupt controller,display card(VGA),sound card,PS2 int
CAR_LI2
- DE1-SOC实验开发板和Verilog HDL语言的交互式程序作品，选择避障小车作为课程设计题目，并根据选题制定了如下设计需求： 1.能实现基本的避障小车功能，即躲避障碍，变速，计分，计时显示游戏开始、进行和结束画面； 2.能实现人机交互功能，玩家可通过外接键盘或DE1-SOC开发板自带按键和开关操作小车转向； 3.能通过VGA在显示屏中显示，并且能达到5Hz的刷新频率； 4.能实现自定义小车和障碍物皮肤的功能；(DE1-SOC experiment development board