搜索资源列表
Altera_DDR_controller_core
- Altera DDR SDRAM控制器完整Verilog代码包，包括Verilog源代码，Doc说明文档，仿真DDR芯片模型，仿真testbench等-Altera DDR SDRAM Controller. Verilog source codes, descr iption documents, DDR verilog model and simulation testbench are all included.
testbench
- 关于如何写Verilog测试台的文档，对于测试程序很有帮助噢-On how to write Verilog test documents, test procedures for helpful Oh
testbench
- 利用system verilog写仿真测试程序，详细介绍system verilog的语法，及教程 -use system verilog write testbench
testbench
- 这是讲述如何编写testbench的，我认为很经典的。值得一看-This is how to prepare Testbench, I think is very classic. Worth a visit
VERILOG-jpeg
- 用Verilog语言在FPGA上实现JPEG图片的解码，附带testbench-With the Verilog language in the FPGA to achieve JPEG image decoding, with testbench
Writing_Testbenches_using_System_Verilog
- Testbench creation and development methodology with System Verilog. By Janick Bergeron.
SPI_FireWall
- verilog spi file with testbench
adder4
- 是用verilog写得加法器以及计数器里面有测试文件（testbench），对于初学者来说这个可以用来参考下-Is written in Verilog adder and counter inside a test file (testbench), for beginners this can be used to reference the next
20081129464173846
- 介绍Verilog HDL, 内容包括： – Verilog应用 – Verilog语言的构成元素 – 结构级描述及仿真 – 行为级描述及仿真 – 延时的特点及说明 – 介绍Verilog testbench • 激励和控制和描述 • 结果的产生及验证 – 任务task及函数function – 用户定义的基本单元(primitive) – 可综合的Verilog描述风格-Introduced the Verilog HDL, in
cascaded_adder
- implementation of cascade adder with verilog plus testbench
TestBench
- 怎样写testbench 本文的实际编程环境：ISE 6.2i.03 ModelSim 5.8 SE Synplify Pro 7.6 编程语言 VHDL 在ISE 中调用ModelSim 进行仿真-、assert (s_cyi((DWIDTH-1)/4) = 0 ) and (s_ovi = 0 ) and (s_qutnt = conv_std_logic_vector(v_quot,DWIDTH)) and (s_rmndr = conv_std_log
Springer_2006_SystemVerilog_for_Verificatio_Chris
- A Guide to Learning the Testbench System Verilog Language Features
verilog_example
- 九个verilog源码例子，包括寄存器，状态机等，含testbench-9 verilog source code examples, including registers, state machines, with testbench
test_bech
- verilog + testbench 文件的读写操作-verilog+ testbench
Testbench(Verilog)
- verilog验证平台的使用 很不错 很详细 想具体-verilog verification platform is more like using a very good specific
testbench(vhdl)
- 是学习数字电路设计verilog语言，及Writing testbench的首先好书。-wrting testbench
verilog
- 这是一个uart串口实现16550的实现，代码已测试过了。-This is a 16550 uart serial port, the code has been tested before.
A-Verilog-HDL-Test-Bench-Primer
- verilog testbench 编写入门，轻松教会编写测试代码-shell interpreter tutorial information, content, round and rich, from the basics
Modsim-AND-testbench
- 关于fpga中，测试平台testbench的技巧，及仿真软件MOSIDISIM-About fpga skills test platform testbench, and simulation software MOSIDISIM
verilog
- 8位计数器，可以实现计数器的相关功能，内涵verilog文件和testbench文件(8 bits counter,include v and testbech files ,has the ability of 8 bits counter)