搜索资源列表
USB枚举
- ALTERA NIOS处理器实验，编程环境是QUARTUS，在NIOS SHELL下编译实现功能。实验USB接口-Altera NIOS processor experiments, programming environment is QUARTUS in NIOS SHELL compiler functionality. Experimental USB interface
USB接口控制器参考设计_xilinx提供_vhdl
- USB接口控制器参考设计，xilinx提供的VHDL源代码-USB interface controller reference design for Xilinx VHDL source code
USB_ReferenceDesign
- 本程序usb的接口程序，用的工具是ISE,实现usb和pc主机之间的通信，所用的USB芯片是FT245BM.-the procedures usb interface procedure, the ISE tools, pc achieve usb and communications between the mainframe, using a USB chip is FT245BM.
实现USB接口功能的VHDL和verilog完整源代码
- 实现USB接口功能的VHDL和verilog完整源代码,Implementation USB interface functions of the VHDL and Verilog source code integrity
Mars-SP3-U_SCH.rar
- 一块XC3S400 FPGA电路板的原理图，板子上有CY7C68013A作为USB接口,A XC3S400 FPGA circuit board schematics, board have CY7C68013A as USB interface
usb_phy.tar
- Very simple USB 1.1 PHY. Includes all the goodies: serial/parallel conversion, bit stuffing/unstuffing, NRZI encoding decoding. Uses a simplified UTMI interface. Currently doesn t do any error checking in the RX section [should probably check f
USBandFPGAjiekou
- USB与FPGA接口的程序设计。里面是所有的源文件都经本人测试可以用，放心下载吧-USB interface with the FPGA programming. Inside are all the source files have been tested, I can use, rest assured that you download
USB
- USB通信协议的硬件描述语言代码，用于FPGA的总线接口控制器开发-USB communication protocol of the hardware descr iption language code for the FPGA bus interface controller development
usbip
- USB接口控制器参考设计，xilinx提供VHDL代码 -USB interface controller reference design, xilinx provide VHDL code
cp_uart_6
- 用CPLD驱动UART转USB芯片CP2102的verilog代码，与PC通信 包括CP2102的配置 驱动等-Using CPLD to drive the USB-UART CP2102 interface. verilog code, then communicate with PC, including the configuration and drivers, etc.
USB
- 用VHDL编写实现的USB接口控制器源码，自带testbench，解压后用ISE打开工程文件即可。-Prepared with the VHDL source code to achieve the USB interface controller, bring their own testbench, after decompression project file can be opened with the ISE.
usb_model
- usb接口model原码设计,可以模拟USB的接口数据接收,用于usb接口数据的仿真.-usb interface model of the original codes designed to simulate USB interface data reception, usb interface data for the simulation.
usb_fpga_1_2_latest.tar
- USB2.0的FPGA内核，使其可以通过FPGA控制CY公司出品的CY7C68013USB微控制器，对USB设备进行读写操作。-• Xilinx Spartan-3 XC3S400 FPGA • High-Speed (480 MBit/s) USB interface via Mini-USB connector (B-type) • Cypress CY7C68013A/14A EZ-USB-Microcontroller • 60 G
usb_wr_Verilog
- fpga ubs通讯模块 verlog语言 使用EZ-USB FX2-USB interface. use EZ-USB FX2 carry out PC communication with FPGA by USB.
USB-to-RS232-adapter-module
- 母板通过FR232R芯片及其外围电路实现USB接口转UART（TTL电平）接口，并提供自定义的双列插针扩展接口；功能子板则分为RS232接口和TTL接口两种，并可根据需要设计RS485/RS422/CAN总线接口。-Motherboard chip by FR232R USB interface and its peripheral circuit switch UART (TTL level) interface, and provide a custom double-row pin exp
The-scheme-of-USB-interface
- 本文采用 USB 接口芯片+FPGA+自行设计的 429 总线驱动电路的方案， 完成了 USB-429 总线接口的设计。其中，USB 接口芯片采用 Cypress 公司的 从设备芯片 CY7C68013，实现了与计算机 USB 总线接口的数据通信。FPGA 代替 429 专用协议收发芯片，完成 429 总线数据的格式转换和协议处理，设 计更为灵活，成本更加低廉-The scheme of USB interface chip+ FPGA+ self-designed 429 bu
USB-COM-routines
- 使用CPLD实现的USB通讯与UART通讯相互转换，USB通讯速率可以达到20M 使用专用USB接口芯片cy7c68013芯片-Using CPLD implementation of USB communication and conversion between UART communication, USB communication speed can reach 20M using the dedicated USB interface chip chip cy7c68013
USB VHDL
- Full USB interface fo FPGA CPLD VHDL
USB Interface IP Core
- This module implements data receiving and transfering with cooperation of PIDUSBD12
ezusb_io_latest.tar
- CY7C68013实现FPGA控制的USB接口通信，已通过测试(CY7C68013 FPGA control to achieve the USB interface communication, has passed the test)