搜索资源列表
aes_core.tar
- AES的Verilog实现,用于加密的算法硬件实现!
AES加密的VHDL源码
- 用VHDL语言实现的AES加密算法的源代码，已经在硬件上下载运行实现了。
VHDL_AES_ZigBee
- 用VHDL实现的ZigBee模块控制算法以及AES加密算法，用于Xilinx的FPGA!-With the realization of VHDL ZigBee module control algorithm and AES encryption algorithms for Xilinx FPGA!
aes
- aes的加密解密算法的源代码以及测试源代码和仿真结果图-aes encryption decryption algorithm source code and test source code and simulation results map
AES256-XILINX10.1
- 用XILINX公司提供的NetFPGA板卡并结合软件Xilinx10.1进行系统设计，采用硬件描述语言Verilog实现了 AES-256加密算法。-Provided by XILINX board combined with software Xilinx10.1 NetFPGA system design, using Verilog hardware descr iption language implementation of the AES-256 encryption algorit
AESverilog
- AES加密算法的Verilog语言实现，通过编译-AES encryption algorithm in Verilog Implementation
SSSSS
- 一种实用的基于FPGA的加密算法的设计，有AES和DES-A practical FPGA-based design of encryption algorithm, AES and DES have
aes-core
- Verilog编写的美国标准加密算法AES的硬件实现包含完整代码及测试程序。- Verilog the compilation American standard encryption algorithm AES hardware realizes contains the complete code and the test order.
aes_core_128bits
- 高级加密算法verilog版,包括加密和解密算法，其中有s盒，行移位，列混淆等具体算法。-aes encryption for verilog，include subbyte,shiftrow,mixcol,addroundkey.
FPGA--AES-algorithm
- 本文介绍了AES 数据加密结构, 以及相关的有限域的知识及简单运算, 提出了一种用FPGA 高速实现AES 算法的方案, 该方 案设计的加密模块支持AES 标准的三种密钥长度: 128,192,256, 支持ECB, CBC, CTR 三种工作模式, 即支持feedback 和non- feedback 两种模式, 最后给出了本设计的性能指标-This article describes the AES data encryption structure, as well as the
aes
- aes加密算法的Verilog语言实现（顶层代码，已编译，无错误）-aes encryption algorithm of Verilog language (top-level code, compile, no error)
AES_verilog
- 对AES算法加密解密的Verilog源代码，可以实现其128位和256位明文密文之间的转换。-AES algorithm for encryption and decryption of Verilog source code, can achieve the conversion of its 128 and 256 between the plaintext ciphertext.
AES
- AES加密和解密算法的硬件语言描述，很值得大家来学习！-AES hardware encryption and decryption algorithm descr iption language, it is worth learning!
AES
- 这是一个AES加密算法的程序，适用verilog hdl语言写的-A AES ALGORITHM
AES
- AES算法部分模块行位移列变换以及主题程序加密解密-AES algorithm transforms part of the module rows and columns relating to the displacement of encryption and decryption program
apbtoaes128_latest.tar
- AES加密算法verilog代码实现，基于APB总线接口数字IP，包含详细的testbench-AES encryption algorithm verilog code, based on the APB bus interface digital IP, contains a detailed testbench
20161227_sf
- AES加密算法中的列混合模块的FPGA实现源代码，采用Verillog语言，在软件Quartus II上综合-AES encryption algorithm in the FPGA column hybrid module implementation source code, using language Verillog integrated in the Quartus II software
aes-128_pipelined_encryption
- AES 加密算法 基于流水线设计 成熟IP core-AES encryption algorithm based on pipeline design mature IP core
AES加密算法密码模块
- 其实现了AES加密中的密码模块，包含了功能的说明，模块以及测试用例，学习上手的难度较小(The realization of the AES encryption password module, contains a descr iption of the function modules and test cases, learning difficult to get started)
各种密码算法的FPGA实现情况
- 各种密码算法的FPGA实现情况 1.AES算法FPGA实现分析 2.DES加密算法的高速FPGA实现 3.RSA加解密运算的FPGA硬件实现研究(FPGA implementation of various cryptographic algorithms)