搜索资源列表
aes
- verilog实现的AES-128加解密程序，FPGA验证通过-verilog implementation of AES-128 encryption and decryption process, FPGA verification through
aes
- aes的加密解密算法的源代码以及测试源代码和仿真结果图-aes encryption decryption algorithm source code and test source code and simulation results map
aes_decrypt
- This the Top Module for AES Decryption algorithm-This is the Top Module for AES Decryption algorithm
test_dec1
- This Module creates the test Bench for AES Decryption Algorithm
FPGA_128_AES_decryption
- 以FPGA具體實現的128-bit AES decryption，包括介紹文件以及源碼。-FPGA-based 128-bit AES decryption
decryption
- AES decryption in VHDL!! Wit LCD controls
AES
- FPGA Implementation of AES Encryption and Decryption
aesall
- AES encryption and decryption
aes
- 此程序完成aes的硬件语言实现部分，通过vhdl语言完成加解密过程。-This process is complete aes hardware language section, vhdl language to complete the encryption and decryption process.
AESzuihou
- 在赛灵思软件ISE上实现的ＡＥＳ加解密算法，并且在ＭＯＤＥＬＳＩＭ上仿真。希望对你有所帮助-The Xilinx software ISE AES encryption and decryption algorithms, and simulation MODELSIM on. I hope for your help
NOIS-II_AES
- 基于NOIS II的AES加解密系统 完整的工程文件 -NOIS II-based AES encryption and decryption of a complete project file system
AES_verilog
- 对AES算法加密解密的Verilog源代码，可以实现其128位和256位明文密文之间的转换。-AES algorithm for encryption and decryption of Verilog source code, can achieve the conversion of its 128 and 256 between the plaintext ciphertext.
AES
- AES算法加解密过程的Verilog代码，包括测试文件，通过FPGA验证。-AES algorithm encryption and decryption process Verilog code, including test files through the FPGA verification.
AES
- AES加密和解密算法的硬件语言描述，很值得大家来学习！-AES hardware encryption and decryption algorithm descr iption language, it is worth learning!
AES
- AES的加密解密verilog全部源代码-AES encryption and decryption verilog full source code
OOO
- AES 低资源利用率的加密解密，状态机的使用，128位的-Encryption and decryption, the state machine of low resource utilization using AES 128-bit
AES
- AES算法部分模块行位移列变换以及主题程序加密解密-AES algorithm transforms part of the module rows and columns relating to the displacement of encryption and decryption program
Coding Files
- We present an efficient hardware architecture design & implementation of Advanced Encryption Standard AES Rijndael cryptosystem. The AES algorithm defined by the National Institute of Standard and Technology NIST of United States has been widely
AES 128 ECB Decryption
- Block mode related AES-EBC Encryption
AES 128 ECB Encryption
- Block mode related AES-EBC Decryption