汇编语言VHDL设计的语言及大量例子汇编语言VHDL设计-Assembly language VHDL design language and a large number of examples

一些常用verilog代码实例，包含组合逻辑电路，时序逻辑电路，和一些复杂电路模块-Some commonly used verilog code examples.Contains the assembly logic circuit, temporal logic circuit, and some complex circuit module

The assembly language program code examples for MSP430f448 and Msp430f438 are described in this zipped file. The easy understanding of simple uart, adc, watchdog,timer program are included