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verilogshejiMiLeJIEMAQI
- 用verilog设计密勒解码器 一、题目： 设计一个密勒解码器电路 二、输入信号： 1． DIN：输入数据 2． CLK：频率为2MHz的方波，占空比为50％ 3． RESET：复位信号，低有效 三、输入信号说明： 输入数据为串行改进密勒码，每个码元持续时间为8μs，即16个CLK时钟；数据流是由A、B、C三种信号组成； A：前8个时钟保持“1”，接着5个时钟变为“0”，最后3个时钟为“1”。 B：在整个码元持续时间内都没有出现“0”，即连续16个时钟保
This VHDL code pertains to the DCO model
- code.doc C.1 DCO LEVEL 2 This VHDL code pertains to the DCO model descr iption in Section 6.5.5. The entity declaration of the level 2 DCO is between lines 18 and 39. The VHDL generics or elaboration-phase parameter constants are declared between
除法器的设计本文所采用的除法原理
- 除法器的设计本文所采用的除法原理是：对于八位无符号被除数A，先对A转换成高八位是0低八位是A的数C，在时钟脉冲的每个上升沿C 向左移动一位，最后一位补零，同时判断C的高八位是否大于除数B，如是则C的高八位减去B，同时进行移位操作，将C的第二位置1。否则，继续移位操作。经过八个周期后，所得到的C的高八位为余数，第八位为商。从图(1)可清楚地看出此除法器的工作原理。此除法器主要包括比较器、减法器、移位器、控制器等模块。-Divider design used in this paper, the p
FSKmodulationanddemodulation
- FSK调制与解调，整个设计基于ALTERA公司的QuartusⅡ开发平台，并用Cyclone系列FPGA实现。所设计的调制解调器具有体积小、功耗低、集成度高、软件可移植性强、扰干扰能力强的特点,符合未来通信技术设计的方向。-FSK modulation and demodulation, the entire design is based on ALTERA' s development platform Quartus Ⅱ, and Cyclone series FPGA implem
DE2_LCM_TV_NTSC
- DE2 S O P C 用硬件语言 描述地 开发板上测试 CLM模块 实现视频传输-DE2 SOPC LCM
CPU
- 实现简单CPU功能的源码，可以实现加减乘除和移位功能，VHDL代码，程序运行在MAX PULS和Quartua上。-The purpose of this project is to design and simulate a parallel output controller (POC) which acts an interface between system bus and printer. The Altera’s Maxplus Ⅱ EDA tool is recommended
sourcefile
- 在Altera公司的Cyclone系列FPGA开发板上试验的按键中断程序，希望对那些学习中断开发的初学者有帮助。 pio_key.v是verilog编写的按键中断程序，对应四个按键，按其中任何一个键都可以发送一个中断； keyint.c是Nios中编写的C程序，用于检测按键的中断，如果检测到中断，会检测是哪个按键按下，从而执行相应的程序！ -In Altera' s Cyclone series FPGA development board interrupt key test
avalon_pwm
- altera公司的PWM设计，非常详细！-altera' s PWM design, very detailed!
lcd_palace
- lcd 显示 welcome it s for lcd 。show welcome it s used vhdl language。c++ also，if you cannot understand please inform me。it s important when you use it。-it s for lcd 。show welcome it s used vhdl language。c++ also，if you cannot understand please inform
clock_niosII
- 用Altera公司的SOPC工具NiosII6.0开发，实现hello_world.c，希望对大家有帮助。-Using Altera' s SOPC tools NiosII6.0 development, implementation hello_world.c, hope to help.
PM7832_IC-ON-LINE.CN
- 这个是分布式基站BBU和RRU的IR接口的接口芯片Datasheet-This is a distributed base station BBU and RRU' s IR interface interface chip Datasheet
uCore_120rel_vhdl_f
- uCore architecture (VHDL and Forth sources). MicroCore s top priority is simplicity and understandability. MicroCore is rooted in the Forth language but it is not confined to execute Forth programs – it is a pretty good general purpose processor an
ofdmbaseband
- the OFDM PHY is adaptive therefore it supports multiple schemes BPSK, QPSK, 16-QAM and 64-QAM for data carriers’ modulation. The constellation diagrams are gray mapped and shows the magnitudes I and Q (In-phase and Quadrature) components of e
digital-clock
- 数字钟是计时仪器，它的功能大家都很熟悉。本实验对设计的电子钟要求为： 1．能够对s(秒)、min(分)和h(小时)进行计时，每日按24h计时制； 2．min和h位能够调整； 3．设计要求使用自顶向下的设计方法。 数字钟的功能实际上是对s信号计数。实验板上可提供2Hz的时钟，二分频后可产生s时钟。数字钟结构上可分为两个部分c计数器和显示器。计数器又可分为s计数器、min计数器和h计数器。s计数器和min计数器由6进制和10进制计数器构成，小时计数器较复杂，需要设计一个24(或12)
PWM_edge
- 有关飞思卡尔的C程序——PWM左对齐，初学16位的单片机-Freescale s C program on left-aligned PWM
PS2
- PS2键盘扫描，.c,.h已封装好，用的单片机是TI公司的Msp430-PS2 keyboard scanning,. C,. H is a good package, with the chip is TI' s Msp430
Chapter-2
- Verilog数字系统设计教程(第2版)”这本书的思考题没有答案，要多做实验和仿真-• Source code of designs in chapters 1 to 8. • Chapter 8 designs include the SAYEH processor, its C Compiler, and its Sort program run files. • Several Designs, including SAYEH, that are
Chapter-3
- Verilog数字系统设计教程(第2版)”这本书的思考题没有答案，要多做实验和仿真-• Source code of designs in chapters 1 to 8. • Chapter 8 designs include the SAYEH processor, its C Compiler, and its Sort program run files. • Several Designs, including SAYEH, that are
Chapter-4
- Verilog数字系统设计教程(第2版)”这本书的思考题没有答案，要多做实验和仿真-• Source code of designs in chapters 1 to 8. • Chapter 8 designs include the SAYEH processor, its C Compiler, and its Sort program run files. • Several Designs, including SAYEH, that are
Chapter-5
- Verilog数字系统设计教程(第2版)”这本书的思考题没有答案，要多做实验和仿真-• Source code of designs in chapters 1 to 8. • Chapter 8 designs include the SAYEH processor, its C Compiler, and its Sort program run files. • Several Designs, including SAYEH, that are