搜索资源列表
Verilog2C++
- 将Verilog代码转换成C++代码的软件，C源代码。-soft for changing Verilog code to c++ code ,c code
tbcpu8bit2
- 极小的CPU的VHDL源代码，仅需要占用32个宏单元的CPLD。除了VHDL源代码还包括了汇编器的C源代码-minimal CPU VHDL source code, only occupy 32 macrocell CPLD. Apart from VHDL source code also includes a compilation of C source code
USBXilinx
- 实现了串行通信接口的全部功能，符合RS-232-C标准的完整UART模块源代码，中文注解，清晰易懂，经过严格仿真测试，绝对好用。-a serial communication interface of all functions, with RS-232-C standard UART modules complete source code, Chinese notes, lucid, after a rigorous simulation tests, absolutely useful.
8051VHDLyuandaima
- 这是用C语言编写的关于8051的VHDL的源代码-This is the C language on the preparation of the 8051 VHDL source code
source7-8
- verilog hdl教程135例:verilog hdl语言类似于C语言，便于学习。本文档带有源代码，7-8章-Verilog HDL 135 cases Guide : Verilog HDL language similar to the C language, to facilitate learning. This document with the source code, 7 - 8
source9-10
- verilog hdl教程135例:verilog hdl语言类似于C语言，便于学习。本文档带有源代码，9-10章-Verilog HDL 135 cases Guide : Verilog HDL language similar to the C language, to facilitate learning. This document with the source code, 9-10
Camera_Interface_Verilog
- 该源代码包是基于片上系统的摄像头接口的Verilog语言程序，它包括以下5部分：RTL源代码，测试平台，软件仿真C代码，FPGA综合时的sdc和ucf文件，说明文档。-This source code package is the camera interface module based on the SoC use Verilog language. It has the following 5 parts: RTL code, testbench, software simulating
c2812rtdxtest_c2000_rtw
- 由MATLAB生成的RTDX的源代码，由模型搭建，然后自动生成DSP的源代码-RTDX generated by MATLAB source code, set up by the model, and then automatically generate DSP source code
dmx512
- DMX512接收程序C源代码，DMX512接收程序-C source code of the receiving program DMX512, DMX512 receiving program
MIT_Video-Scaler
- MIT的video scaler论文，文章后面附有c和verilog程序源代码，分为水平缩放和垂直缩放-MIT video scaler papers, articles, source code attached to the back, divided into horizontal scaling and vertical scaling
source3-6
- verilog hdl教程135例:verilog hdl语言类似于C语言，便于学习。本文档带有源代码，3-6章-Verilog HDL 135 cases Guide : Verilog HDL language similar to the C language, to facilitate learning. This document with the source code, 3-6
source11-12
- verilog hdl教程135例:verilog hdl语言类似于C语言，便于学习。本文档带有源代码，11-12章-Verilog HDL 135 cases Guide : Verilog HDL language similar to the C language, to facilitate learning. This document with the source code 11-10-12 Cap
display_control
- 一个LCD控制器的verilog源代码，可以方便的控制TFT LCD！-An LCD controller Verilog source code, can easily control TFT LCD!
source_code
- 一个用c语言编写的自动售货机控制器源代码-A with c language source code for vending machine controller
hdlc
- HDLC协议控制器，用FPGA实现的verilog源代码-HDLC protocol controller, implemented with FPGA verilog source code
SPWM
- 用C语言 并利用FPGA来进行SPWM 包含详尽的源代码-Using C language and use of FPGA to be SPWM source code contains detailed
uart
- 用单片机控制tc35的初始源代码 c格式文件-SCM tc35 with the initial source code c format
timer-pwm
- 基于dspic30f2010芯片的定时器模块以及输出比较模块产生可调PWM波C程序源代码-Chip timer module based dspic30f2010 and adjustable output compare module PWM wave generated C source code
iic总线源代码
- 此文件是iic总线驱动的源代码文件，iic.c 可以读写控制多个挂在总线上的器件。
iic_v2_00_a
- 基于赛林思FPGA的IIC接口设计，支持主机、从机、多主机通信的总线特性，包括datasheet，C语言源代码。-Sailin Si FPGA-based IIC interface design to support the host from the machine, multi-master communication bus features, including the datasheet, C language source code.