搜索资源列表
jtag0
- 本程序使用vhdl编写的jtag接口实现程序,其中有些功能未能实现,希望有人能够帮忙完善!-vhdl the procedures used to prepare the jtag interface procedures, which some of them did not materialize, hope someone can help perfect!
vhdl_vga
- 彩条信号发生器使用说明 使用模块有：VGA接口、脉冲沿模块、时钟源模块。 使用步骤： 1. 打开电源+5V 2. 信号连接，按下表将1K30信号与实际模块连接好。 3. 1K30板连接好并口线，并将程序加载。 4. 将彩色显示器的线与VGA接口连接好。 5. 彩条信号就可以在显示器中产生，通过脉冲沿模块按键MS1可以改变产生彩条的 -color of the signal generator for use with the use of modules : V
mp3if
- 通过CPLD将8位并行数据转换为串行数据并可以采用I2C方式与其他器件连接，可以用于MCU需要与提供I2C接口器件通信的场合。-through CPLD to eight parallel data into serial data and methods can be used I2C connections with other devices, which can be used to provide MCU with I2C Interface Communications occasi
xapp368
- 可编程器件厂商Xilinx的手持式逻辑分析仪的逻辑设计，包括完整的可用于Xlinx器件的硬件code，以及用来接口的C代码-makers Xilinx programmable devices, handheld logic of the logic analyzer design, including complete Xlinx device can be used for the hardware code, and to interface C code
cpldcontrol
- 一段cpld的控制程序，可以进行传并转换，读写接口，每秒64k-a cpld control procedures can be done - and switching to read and write interface per second 64k
ps2_soc2
- PS2的源代码VHDL语言实现，可以和计算机直接连接．做鼠标键盘接口．-PS2 source VHDL, and can be connected directly to the computer. So the mouse, keyboard interface.
miniuart_vhdl
- 用VHDL硬件描述语言开发的miniUART接口IP Core,用户可以将其嵌入到自己的FPGA模块中。-VHDL hardware descr iption language developed by miniUART Interface IP Core, Users can be embedded into their own FPGA module.
I486bus
- 基于VHDL语言开发的I486总线接口程序。实现了一个三态的总线，可保证数据的正常传输。-based on VHDL development of the I486 bus interface procedures. Implementation of a three-state bus can ensure that the normal data transmission.
SPI_verilogHDL
- 本原码是基于Verilog HDL语言编写的，实现了SPI接口设计，可以应用于FPGA,实现SPI协议的接口设计.在MAXII编译成功,用Modelsim SE 6仿真成功.-primitive code is based on Verilog HDL language, and achieving the SPI interface design, FPGA can be used to achieve agreement SPI interface design. MAXII success
IIS_VHDL
- VHDL实现了IIS接口程序，在Quartus II 6.0上编译通过，在板子上可以读取IIS数据-IIS VHDL interface procedures, the Quartus II 6.0 compiled by the board can read data IIS
leon3-altera-ep2s60-ddr
- This leon3 design is tailored to the Altera NiosII Startix2 Development board, with 16-bit DDR SDRAM and 2 Mbyte of SSRAM. As of this time, the DDR interface only works up to 120 MHz. At 130, DDR data can be read but not written. NOT
Verilog.Verilog编写的出租车计价器程序
- Verilog编写的出租车计价器程序，可以设置按路程计价，按等待时间计价。非常方便，界面良好,Verilog program, prepared a taxi meter can be set according to distance pricing, valuation by waiting time. Very convenient, good interface
同有SPI接口的器件进行通信对SPI接口器件的读写控制vhdl源程序
- vhdl实现spi可以同有SPI接口的器件进行通信对SPI接口器件的读写控制vhdl源程序，fpga cpld-vhdl spi can achieve devices with a SPI interface to communicate with devices on the SPI interface to read and write vhdl source code control
VHDL-SPI-Module.doc
- 本spi参数化通讯模块是一个支持SPI串行通信协议从协议的SPI从接口。可通过改变参数设置传输的位数，由外部控制器给定脉冲控制传输。-The parameters of spi communication module is a support SPI serial communication protocol from the agreement from the SPI interface. By changing the parameter settings can be transmit
ps2
- vhdl实现ps2接口的程序,可以接受键盘的输入或者鼠标的输入.-VHDL procedures to achieve ps2 interface can accept keyboard input or mouse input.
SPI_Interface
- SPI接口的vhdl代码，可以实现与单片机的spi通信，完整的工程-SPI interface of the VHDL code can be achieved with SCM spi communication, complete works
FPGA-VGA-interface
- 基于FPGA的VGA接口显示程序，可显示三种彩色条纹-FPGA-based interface VGA display program can display the three color stripes
canbus
- CAN通信协议的硬件描述语言代码，用于FPGA的总线接口控制器开发-CAN communication protocol of the hardware descr iption language code for the FPGA bus interface controller development
interface
- 单片机和CPLD的接口实现，能够实现数据的读写。-MCU and CPLD' s interface can read and write data.
custom_periph
- vhdl can controller for can interface