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OFDM
- this code is for orthogonal frequency devision multiplexing and it is essential for the communication blocks-this code is for orthogonal frequency devision multiplexing and it is essential for the communication blocks
RAM
- this code is for the ram blocks and it is very essential if you are going to implement asic
11912890arith_lib_cadence
- VHDL中的一些常用功能块，源码，以及一些常用库，好多好多的。-VHDL some of the common functional blocks, source code, as well as some common libraries, many many of the.
VerilogCodingStyle
- This document describes coding styles and guidelines for writing Verilog code for ASIC blocks and test benches.
huffmandecoder_latest.tar
- huffman decoder and encoder blocks fully generated in vhdl code.hope it helps
Simulink-to-VHDL-Route
- This paper presents the way of speeding up the route from the oretical design with Simulink/Matlab, via behavioral simulation in fixed-point arithmetic to the implementation on either FPGA or custom silicon. This has been achieved by porting
AssignmentP6
- 1. For the VHDL model given below (Code List One), compare the FIFOs implementations on CPLD and FPGA. (1) Synthesize and verify (simulate) the VHDL design of the FIFOs (2) For CPLD implementation (fit) of the FIFOs, how many MCs (macrocells)
ADPLL
- This paper presents the ADPLL design using Verilog and its implementation on FPGA. ADPLL is designed using Verilog HDL. Xilinx ISE 12.1 Simulator is used for simulating Verilog Code. This paper gives details of the basic blocks of an ADPLL. In this p
ex9_cof_M4K_test1
- FPGA器件中通常嵌入一些用户可配置的存储块，此代码是关于基M4K块的单RAM配置仿真实验。 -FPGA devices are usually embedded memory blocks some user-configurable, this code is based on a single M4K block RAM configuration simulation.
Camera_Logic
- 双目视觉成像，双目视觉摄像头，3D摄像头对应的FPGA图像采集逻辑程序。1> 适用于：单目和多目视觉系统。2> 附图为双摄像头系统，应用了两条图像控制流水，源码对应图中红色的逻辑块，本人已实测代码为OK。-Imaging binocular vision, binocular vision camera, 3D camera image acquisition corresponding FPGA logic program. Applies to: monocular vision