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VHDL_Examples_for_education
- VHDL代码编程,集合了众多优秀的实例,胜过任何一本书的例子,作为教学或程序开发中调用非常合适!-VHDL code programming, a combination of a large number of outstanding examples are better than any one book's examples, as a teaching program or call very appropriate!
keyboard4_4
- 该代码是4乘4标准键盘扫描程序的源代码，用VHDL编写的，我在调试的时候忘记设置复位键了，大家也要注意了-The code is 4 x 4 standard keyboard scan a program's source code, prepared by the use of VHDL, I remember when debugging set the reset button, we have to pay attention to the
XAPP678c
- xinlinx s vhdl code model and user guider-xinlinx's vhdl code model and the guiding user
引爆器
- 数字密码引爆器的输入描述：1、 在开始输入密码以前的等待状态，首先要按READY键，表示目前准备就绪，可以输入数字密码；2、 当引爆事件发生后，应该回到等待状态，设置WAIT_T键；3、 如果输入密码不正确，此时要操作READY和WAIT_T是不起作用的，必须由设计人员重新设置到等待状态，设置SETUP键，SETUP为内部按键，操作人员应该不能接触；4、 确定密码输入后，要设计一个点火按键FIRE；-digit passwords detonated's input Descr ipti
dual_RAM.rar
- actel fusion startkit FPGA开发板试验例程，可实现2k8的双口ram，实现数据存储，缓冲。包含verilog HDL 语言源码,actel fusion startkit FPGA development board test routines, can be realized 2k8' s dual-port ram, achieving data storage, buffer. Language source code contains the verilog
abs_code.rar
- 这是用CPLD开发的读取绝对式编码器反馈的信号的代码，读取电机的转子的绝对位置和判断转动方向对于电机控制很实用。,This is read by the CPLD Development absolute encoder feedback signal to the code, read the motor' s rotor position and to determine the absolute direction of rotation is very useful for mot
LCD12864
- 1 fpga驱动lcd液晶12864的verilog源程序 (显示英文，可以在源程序中直接修改成自己想要显示的英文) 2 引脚配置完成，程序已经测试，完全好用 3 使用的FPGA芯片是altera的max2EP2C5T1-1 fpga driver' s verilog source code 12864 lcd LCD (display in English, you can directly modify the source program into what you w
This VHDL code pertains to the DCO model
- code.doc C.1 DCO LEVEL 2 This VHDL code pertains to the DCO model descr iption in Section 6.5.5. The entity declaration of the level 2 DCO is between lines 18 and 39. The VHDL generics or elaboration-phase parameter constants are declared between
NIOS_LM240160
- 基于NIOS的，TOPWAY公司的LCD液晶---LM240160 驱动程序。-Based on NIOS' s, TOPWAY company‘s LCD--- LM240160 driver code.
link_port-v1[1].1.0
- 用于测试ADI的TS201与FPGA之间通信的LINK程序，压缩文件内包括VHDL和Verlog代码。-ADI is used to test the communication between the TS201 and the FPGA' s LINK program, compressed file to include VHDL and Verlog code.
RS-code
- 我测试过的！Verilog HDL实现RS编码。-I' ve tested it! RS coding Verilog HDL implementation.
i8255_verilog
- 8255的Verilog hdl源代码，适合FPGA工程师使用-8255' s Verilog hdl source code for FPGA engineers
recuart_50m
- 本代码功能为实现接收PC发送的串口数据功能 程序通过quartusII 8.1编译，使用verilog语言编写。 可在彬杰科技*BJTECH公司基于altera epm240的开发板上验证。 （开发板网址http://item.taobao.com/auction/item_detail-0db1-69fe7069aa3ba544abf783bc4427b377.htm） 有需要的朋友可以下载参考-The code functions to achieve the receivi
SDRAM
- 用FPGA实现对sdram读写的源代码，芯片用的是Altera公司的，需要的同学可以看看！-FPGA realization of sdram read and write the source code, the chip using Altera' s, students need to take a look!
turbodecoder
- 用vhdl实现turbo码的迭代解码，转某N人的程序-Using vhdl implementation of iterative decoding turbo codes, transfer of a person' s procedures for N
RS485EN
- RS485的双向通信处，正在为此头疼的同学们可要注意了，这个可以解决你们双向通信过程中的很多问题哦-Two-way RS485 communications, the headache is to this end they' ll pay attention to the students, this two-way communication you can solve many problems in the course of oh
URAT_VHDL_CODE
- altera公司的fpga源代码，用VHDL编写的uart程序。-altera' s fpga source code, uart program written using VHDL.
VHDL
- 双口RAM模块源代码（VHDL）,用于开发FPGA的双口RAM，可以直接下载到工程中使用。-Dual-port RAM module source code (VHDL), for the development of FPGA' s dual-port RAM, can be directly downloaded to the project use.
AD0819
- 利用verilog语言实现对AD0819的模数转换控制，源代码工程文件-Verilog language used on the AD0819' s ADC control, source code project files
sdfsdFifo
- 这是一个异步fifo的Verilog 代码，该代码的功能是实现异步的first in first out-This is an asynchronous fifo in the Verilog code, the code' s function is to achieve asynchronous first in first out