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NIOS_TFT
- 用Quartus II 8.0（32bit），NIOS编译环境下，用TFT做的一个数码相框，附加原理图和veri-log程序代码-Using Quartus II 8.0 (32bit), NIOS compiler environment, TFT do with a digital photo frame, attached schematic and program code veri-log
FPGA_COM
- FPGA实现的多串口程序(支持收发中断，QUARTUSII编译),各串口独立-FPGA serial program (support to send and receive interrupt, QUARTUSII compiler), the serial independence...
lcd1602
- 1602液晶显示程序，+万年历显示。，你懂得-1602 LCD program,+ calendar display. ICC compiler, you know
Chapter-2
- Verilog数字系统设计教程(第2版)”这本书的思考题没有答案，要多做实验和仿真-• Source code of designs in chapters 1 to 8. • Chapter 8 designs include the SAYEH processor, its C Compiler, and its Sort program run files. • Several Designs, including SAYEH, that are
Chapter-3
- Verilog数字系统设计教程(第2版)”这本书的思考题没有答案，要多做实验和仿真-• Source code of designs in chapters 1 to 8. • Chapter 8 designs include the SAYEH processor, its C Compiler, and its Sort program run files. • Several Designs, including SAYEH, that are
Chapter-4
- Verilog数字系统设计教程(第2版)”这本书的思考题没有答案，要多做实验和仿真-• Source code of designs in chapters 1 to 8. • Chapter 8 designs include the SAYEH processor, its C Compiler, and its Sort program run files. • Several Designs, including SAYEH, that are
Chapter-5
- Verilog数字系统设计教程(第2版)”这本书的思考题没有答案，要多做实验和仿真-• Source code of designs in chapters 1 to 8. • Chapter 8 designs include the SAYEH processor, its C Compiler, and its Sort program run files. • Several Designs, including SAYEH, that are
Chapter-6
- 练习六在verilog hdl中使用函数317 -• Source code of designs in chapters 1 to 8. • Chapter 8 designs include the SAYEH processor, its C Compiler, and its Sort program run files. • Several Designs, including SAYEH, that are programmed on
Chapter-7
- 练习七在verilog hdl中使用任务（task）319 -• Source code of designs in chapters 1 to 8. • Chapter 8 designs include the SAYEH processor, its C Compiler, and its Sort program run files. • Several Designs, including SAYEH, that are program
Chapter-8
- 练习八利用有限状态机进行时序逻辑的设计322 -• Source code of designs in chapters 1 to 8. • Chapter 8 designs include the SAYEH processor, its C Compiler, and its Sort program run files. • Several Designs, including SAYEH, that are programmed on
IR
- FPGA实现的红外IR解码程序，已成功通过Quartus编译，可实现红外正确接收和数据解码提取。-This is a verilog IR decoding program. It has been already compiler through the QuartusII.
STC-GY-27-ADXL345-IIC
- STC-GY-27-ADXL345 IIC测试程序 // GY-29 ADXL345 IIC测试程序 // 使用单片机STC89C51 // 晶振：11.0592M // 显示：LCD1602 // 编译环境 Keil uVision2-STC-GY-27-ADXL345 IIC test program// GY-29 the ADXL345 the IIC test program// use microcontroller STC89C51// crystal: 11
SoftDrink
- 用Verilog编写的自动售货机控制程序，在cyclon DE2开发板上测试通过，建议用Quartus 10.1编译。-Vending machine control program written using Verilog test by in cyclon DE2 development board, we recommend using Quartus 10.1 compiler.
uart_verilog
- Verilog HDL语言编写的uart程序，在别人基础上改动和优化完成，quartus ii 10.0编译通过，可综合，板上仿真通过。将PC机发送的字符串发送回，可一次发送多个字符串。-Verilog HDL language uart program, in others on the basis of changes and optimization is complete, quartus ii 10.0 compiler, integrated, on-board through si
UART
- Verilog HDL编写的串口程序实例，很详细好用的参考代码。针对Xilinx FPGA开发板，在Xilinx ISE编译调试成功，串口开发的经典例程。-Verilog HDL serial program written examples, very good reference code in detail. In view of the Xilinx FPGA development board, in Xilinx ISE compiler debugging success, a s
03_key_detect_1
- 该程序为按键防抖程序，编译环境为Quartus/Xilinx，使用语言为VerilogHDL-The program for key stabilization program, the compiler environment Quartus/Xilinx, use language VerilogHDL
07_number_mod
- 该程序为数码管程序，编译环境为Quartus/Xilinx，使用语言为VerilogHDL-The program for the digital program, the compiler environment Quartus/Xilinx, use language VerilogHDL
16_buzzer
- 该程序为蜂鸣器程序，编译环境为Quartus/Xilinx，使用语言为VerilogHDL-The program for the buzzer, compiler environment for Quartus/Xilinx, use language VerilogHDL
25_lcd_system
- 该程序为lcd程序，编译环境为Quartus/Xilinx，使用语言为VerilogHDL-The program for lcd, compiler environment for Quartus/Xilinx, use language VerilogHDL