Xilinx Design Flow Device capabilities are worthless if you can’t use them in YOUR course • Design software should support all ranges of designs from CPLD to the high-density FPGA • Works with YOUR design flow – minimize impacts

USB 1.1 slave/device IP core. Default configuration is 6 endpoints: 1 Control, 1 Isochronous IN, 1, Isochronous Out, 1 Bulk IN, 1 Bulk Out, 1 Interrupt IN. Includes control engine, providing full enumeration process in hardware - no external mi