用FPGA实现的JPEG压缩器，可以直接使用，内含完整文档说明-This project features a complete JPEG Hardware Compressor (standard Baseline DCT, JFIF header) with 2:1:1 subsampling, able to compress at a rate of up to 24 images per second at the maximum resolution 352x288 (on XC2V

用verilog硬件语言实现了动态huffman编码，能够压缩字符串文件，展示了硬件的压缩率-Using verilog hardware descr iption language to achieve a dynamic huffman coding to compress the string file, showing the hardware compression rate