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N-0.5fenpinqi
- vhdl N-0.5分频方法设计，可以输入任意数值N，即分得到N－0.5的频率。-vhdl N - 0.5-frequency method, we can input arbitrary numerical N, namely, to be N - 0.5 frequencies.
9.1_ONE_PULSE
- 基于Verilog-HDL的硬件电路的实现 9.1 简单的可编程单脉冲发生器 9.1.1 由系统功能描述时序关系 9.1.2 流程图的设计 9.1.3 系统功能描述 9.1.4 逻辑框图 9.1.5 延时模块的详细描述及仿真 9.1.6 功能模块Verilog-HDL描述的模块化方法 9.1.7 输入检测模块的详细描述及仿真 9.1.8 计数模块的详细描述 9.1.9 可编程单脉冲发生器的系统仿真
minus
- 一位二进制全减器的设计，分别用原理图输入法和文本输入法，用分层设计的方法完成-A binary full subtractor design, respectively, schematic input and text input method, complete with a hierarchical design method
counter
- 利用EDA工具MAX-PlusII的VDHL输入法，输入VHDL程序，实现2位计数器，在七段译码器上以十进制显示：0、1、2、3、0、...。时钟信号使用83管脚。采用自动机状态转换方式设计该计数器；建立相应仿真波形文件，并进行波形仿真；分析设计电路的正确性。-The use of EDA tools VDHL of the MAX-PlusII input method, enter the VHDL program, the realization of two counters, in t
intfit
- 基于Farrow结构的平方内插器，其中输入为8位的小数插值相位和8位的输入数据，实现8位数据输出，仿真验证结果显示此种方法占用资源少。-Farrow structure based on the square interpolator, which enter the decimal for the 8-bit and 8-phase interpolation of the input data to achieve 8-bit data output, simulation results
5
- 4*4矩阵状态机键盘 是数字电路设计中常用的信号输入法-4* 4 matrix keyboard state machine is commonly used in digital circuit design, signal input method
seven
- 基于VHDL实现输入控制7段数码管的代码，分别用逻辑表达式法和真值表法实现。-VHDL-based implementation of digital control input control 7-segment code, respectively, a logical expression method and truth table method to achieve.
speed_measure_on_7_segment
- Period method of frequency measuring (change constant to speed measure). DE2 Board Quartus project. Input signal on GPIO, result on 7seg, start/stop with key[0].
FullAdder
- 要求在Quartus II软件，利用VHDL完成层次式电路设计，电路中的元件可以用VHDL设计也可以用库元件连线构成再封装。借助EDA工具中的综合器，适配器，时序仿真器和编程器等工具进行相应处理。输入方法不限制。适配采用Cyclone系列的EP1C6Q240C8。要求综合出RTL电路，并进行仿真输入波形设计并分析电路输出波形。要求采用层次式结构设计。-Quartus II software requires the use of VHDL complete hierarchical circui
ww1
- 本例实现的检测是否有三路信号输入，如果有可输出一个高电平，同时可计算第一路与第三路之间相差的脉冲数，使用vhdl语言与图形结合的方法。-Achieved in this case detect three-way signal input, if there is a high output, while the first road and calculate the difference between the third way of pulses, using vhdl languag
EDA1
- 完成一位二进制全减器的设计，采用文本输入法分别实现，分层设计，底层采用半加器和逻辑门实现。-Completion of a binary full subtracter design, implementation, respectively, using the text input method, hierarchical design, are based on half adder and logic gates.
subber
- 完成一位二进制全减器的设计，采用原理图输入法和文本输入法分别实现，分层设计，底层由半加器（也用原理图输入法）和逻辑门组成-Completion of a binary full subtracter design, the use of schematic and text input method input method were realized, hierarchical design, the bottom of the half adder (also used schematic
22222222222
- 地址线为8位，数据线为八位的正弦信号发生器，采用文本原理图混合输入的方法。-8-bit address lines, data lines for the eight sinusoidal signal generator, using the text input method for mixed schematic.
test2
- 共阴极七段显示译码电路，EDA用文本输入法设计1位异步清零同步时钟使能的十进制计数器-Seven of the cathode here shows decode circuitEDA use text input method design a asynchronous reset synchronous clock that can counter the decimal
VHDL-program--samples-book
- VHDL程序实例集，其主要内容包括：用VHDL设计的组合电路、时序电路、数字综合电路、电路图输入法要领概述、实用VHDL语句等。-VHDL instance set, the main contents include: VHDL design of combinational circuits, sequential circuits, digital integrated circuit schematic input method essentials outlines, practica
eda6
- 以Altera公司的MAX+plus II为工具软件，采用Verilog HDL文本输入设计法设计8位二进制加减计数器，生成元件符号-Altera s MAX+plus II tools software, using Verilog HDL text input method to design8 binary addition and subtraction counter, generating element symbol
eda-Lab-report
- 三线八线译码器、数据选择器、数据比较器、二进制编码器、译码器的verilog语言输入方法-Three line eight line decoder, data selector, comparator, the binary encoder and decoder of verilog language input method
PLL
- 基于FPGA的锁相环应用，原理图输入法，较为直观，锁相的效果无抖动-FPGA-based PLL applications, schematics input method, more intuitive, the effect of jitter PLL
Verilog_seg7
- Quartus的原理图和.v文件混合输入编程-The mixed input method of schematic File and Verilog HDL File for Quartus II
decoder
- 采用VHDL语言输入法，根据HDB3码编解码规则，确定HDB3码编画出HDB3码的程序设计流程图。编写VHDL源程序、调试及仿真时序波形 -Using VHDL language input method, according to the HDB3 encoding and decoding rules that determine HDB3 code HDB3 encoding and draw a flow chart programming. Write VHDL source co