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Test_Plg_18
- 基于FPGA的等精度频率测试仪,测量范围1HZ到100M.已调试成功.采用康芯公司的FPGA开发板,嵌入51内核程序.-FPGA-based test instrument such as the frequency accuracy, measurement range 1HZ to 100M. Has been a successful debugging. Using Kang' s FPGA core development board, embedded in 51 kernel
socdesignandtest
- SoC是系统级集成，将构成一个系统的软/硬件集成在一个单一的IC芯片里，它一般包含片上总线、MPU核、SDRAM/DRAM、FLASH ROM、DSP、A/D、D/A、RTOS内核、网络协议栈、嵌入式实时应用程序等模块，同时，它也具有外部接口，如外部总线接口和I/O端口。通常，SoC中包含的一些模块是经过预先设计的系统宏单元部件（Macrocell）或核（Cores） ，或者例程（Routines），称为IP模块，这些模块都是可配置的，因此，基于SoC的设计方法学也称为基于IP的嵌入式系统设计
led_flow
- 基于niosII实现的控制流水灯的小系统，对于sopc初学者理解sopc概念以及pio内核很重要-To achieve control based on niosII small light water system, for beginners to understand sopc sopc concept is very important and pio kernel
PWM
- verilog描述 PWM IP核 内部包括载波 占空比 和时能寄存器-IP kernel of PWM based on Verilog hdl
SOPC_watch
- 基于ALtrafpga的niosii内核verilog语言实现的可编程电子钟，需要外接lcd屏幕-Programmable electronic clock, based on the the ALtrafpga the kernel niosii verilog language to achieve an external lcd screen
Verilog-code
- 基于cyclone 内核的fpga的源代码，带quartus2下载文件-Based on the source code of the cyclone kernel fpga, with quartus2, download files
kb
- 基于niosII系统的PS2键盘测试程序，测试PS2键盘与niosII内核的通信是否成功。该程序在Quartus自带的eclipes下编译运行。-Based nios II system PS2 keyboard test procedures, test PS2 keyboard and niosII kernel communication is successful. Compile and run under Quartus comes eclipes.
SP605_V4_beifen_V2_success
- 基于FPGA内核microblaze的开发，使用的开发板是SP605，采用双备份冗余设计，实现了开发板上灯的控制。-Based on FPGA kernel MicroBlaze development, using the development board is SP605, the use of dual redundancy design, to achieve the development of the board on the light control.
noise
- 使用FPGA搭建NOISE||内核，在内核基础上进行工程建立。(Using the FPGA to build NOISE || kernel, based on the kernel to build the project.)
rtl
- 基于S10新品的2x2矩阵乘模块，附带双精度的乘法，除法ip核(2x2 matrix multiplication module based on S10 new product, with double precision multiplication, division IP kernel)