搜索资源列表
firmatlab
- fir在dspbuilder下产生VHDL源码及其测试激励文件时的matlab模型,在modelsim下仿真通过-fir in dspbuilder VHDL source code under test and document the incentive mat lab model, the simulation under through modelsim
fftmatlab
- fft在dspbuilder下产生VHDL源码及其测试激励文件的matlab模型,在modelsim下仿真通过-fft in dspbuilder under VHDL source code and test incentives document matl ab model, the simulation under through modelsim
ddsmatlab
- dds在dspbuilder下产生VHDL源码及其测试激励文件的matlab模型,在modelsim下仿真通过-dds dspbuilder under the VHDL source code and test incentives document matl ab model, the simulation under through modelsim
mxuliematlab
- m序列在dspbuilder下产生VHDL源码及其测试激励文件的matlab模型,在modelsim下仿真通过-m sequence in dspbuilder under VHDL source code and test incentives document matl ab model, the simulation under through modelsim
sinmdlmatlab
- 正弦波在dspbuilder下产生VHDL源码及其测试激励文件的matlab模型,在modelsim下仿真通过-sine wave in dspbuilder under VHDL source code and test incentives document matl ab model, the simulation under through modelsim
02_SynthesizableMATLAB
- Lab 2 – Synthesizable MATLAB This lab exercise will explore the effects that different MATLAB coding styles have on hardware. The lab has two parts, each of which begins with a short introduction. This lab exercise is based on the simple MATLAB FIR
pll.rar
- 模拟锁相环（apll）的一些simulink模型,Analog phase-locked loop (apll) some simulink model
c2812rtdxtest_c2000_rtw
- 由MATLAB生成的RTDX的源代码，由模型搭建，然后自动生成DSP的源代码-RTDX generated by MATLAB source code, set up by the model, and then automatically generate DSP source code
FPGA_DDS
- 基于FPGA的DDS信号发生器产生VHDL源码及其测试激励文件的matlab模型,在modelsim下仿真通过-FPGA-based VHDL source DDS signal generator and the test stimulus file matlab model simulation in modelsim adopted under
QAM16_demo
- This a demonstration for 16QAM. It is a Simulink model, including hardware implementation on Xilinx FPGA for adaptive equalizer and carrier recovery. -This is a demonstration for 16QAM. It is a Simulink model, including hardware implementation on Xil
Simulink-to-VHDL-Route
- This paper presents the way of speeding up the route from the oretical design with Simulink/Matlab, via behavioral simulation in fixed-point arithmetic to the implementation on either FPGA or custom silicon. This has been achieved by porting
FPGA-signal-procession(-MATLAB)
- 基于MATLAB 的FPGA 数字信号处理模块的设计-design of the FPGA signal procession model based on MATLAB
DDS
- 这个是在quartusii和matlab simulink下搭的dds的模型，已经经过仿真是可以的。并且已经转为vhdl代码。-This is quartusii and matlab simulink model to catch the dds, has been the simulation is possible. And has to vhdl code.
Controllable-sine-signal-generator
- 通过MATLAB的SIMULINK模型设计，实现可控正弦信号发生器，并通过DSP BUILDER中的SIGNAL COMPILER转换成QuartusII工程，并实现硬件的下载。-Through the MATLAB SIMULINK model design, realization controllable sine SIGNAL generator, and through the DSP BUILDER of SIGNAL COMPILER converted into QuartusI
systolic--matrix-inversion
- DSP算法架构及设计，内容为基于systolic的上三角矩阵求逆电路的实现，里面有详尽的MATLAB/SIMULINK 仿真模型，及HDL代码和在modelsim中的仿真程序，非常不错的。-Architecture and design of DSP algorithms, based on systolic upper triangular matrix inverse circuit to achieve detailed MATLAB/SIMULINK model and the HDL
liushuideng
- 利用system generator生成的流水灯verilog代码，matlab的model文件也在其中。在spartan3A上验证通过-The verilog code system generator to generate light water Matlab model file also. Spartan3A on validation by
nn_last
- Neural Network with FPGA and VHDL codes + Matlab model
matlabtomodelsim
- matlab to model sim converter coding of vhdl code ypu want to convert that matlab into the xilinx platform model sim simulator
wireless_FPGAcode
- 无线通信模块设计FPGA代码 包括matlab模型文件及verilog源代码-The wireless communication module design including FPGA code matlab verilog model file and source code
kengtentui
- matlab implements five gray correlation degree computing model, Decoupling, restore the original signal, Including compression ratio, image restoration computing uptime and peak signal to noise ratio.