搜索资源列表
firmatlab
- fir在dspbuilder下产生VHDL源码及其测试激励文件时的matlab模型,在modelsim下仿真通过-fir in dspbuilder VHDL source code under test and document the incentive mat lab model, the simulation under through modelsim
fftmatlab
- fft在dspbuilder下产生VHDL源码及其测试激励文件的matlab模型,在modelsim下仿真通过-fft in dspbuilder under VHDL source code and test incentives document matl ab model, the simulation under through modelsim
ddsmatlab
- dds在dspbuilder下产生VHDL源码及其测试激励文件的matlab模型,在modelsim下仿真通过-dds dspbuilder under the VHDL source code and test incentives document matl ab model, the simulation under through modelsim
mxuliematlab
- m序列在dspbuilder下产生VHDL源码及其测试激励文件的matlab模型,在modelsim下仿真通过-m sequence in dspbuilder under VHDL source code and test incentives document matl ab model, the simulation under through modelsim
sinmdlmatlab
- 正弦波在dspbuilder下产生VHDL源码及其测试激励文件的matlab模型,在modelsim下仿真通过-sine wave in dspbuilder under VHDL source code and test incentives document matl ab model, the simulation under through modelsim
color_converter.tar
- 此代码实现不同图像颜色制式之间的相互转换,如XYZ<->RGB, 不同标准的RGB<->RGB 以及RGB<->YCbCr之间的转换,包内含有matlab仿真代码m文件、VHDL代码.v文件以及modelsim仿真的testbench文件,相信对大家有一定的帮助
DCT
- altera fpga verilog 设计的基于查找表的DCT程序及zigzag扫描程序,已经过matlab 和modelsim 验证,文件中包含TESTBENCH ,直接可用
FPGA_DDS
- 基于FPGA的DDS信号发生器产生VHDL源码及其测试激励文件的matlab模型,在modelsim下仿真通过-FPGA-based VHDL source DDS signal generator and the test stimulus file matlab model simulation in modelsim adopted under
filter_VHDL
- 用VHDL语言实现滤波的设计,并通过modelsim仿真!用matlab产生输入结果,并与matlab输出结果比较是相同的.-Filter by language VHDL design and simulation through modelsim! Results with matlab generate input and output compared with the matlab are the same.
histogram4
- 利用matlab和modelsim完成了用直方图均衡化处理灰色图片的前仿真,有处理前后图片的对比,verilog语言编写,但到用实时处理还差很远-Completed using matlab and modelsim deal with the gray image histogram equalization before the simulation, a comparison of before and after pictures, verilog language, but with
sdr
- 全数字OQPSK解调算法的研究及FPGA实现 论文介绍了OQPSK全数字接收解调原理和基于 软件无线电设计思想的全数字接收机的基本结构,详细阐述了当今OQPSK数字 解调中载波频率同步、载波相位同步、时钟同步和数据帧同步的一些常用算法, 并选择了相应算法构建了三种系统级的实现方案。通过MATLAB对解调方案的 仿真和性能分析,确定了FPGA中的系统实现方案。在此基础上,本文采用Verilog HDL硬件描述语言在Altera公司的QuartusⅡ开发平台上设计
view_quartus_simu_on_matlab
- 在进行Quartus仿真时,由于直接用自带的仿真工具无法查看正弦波,将仿真数据另存为tbl格式,用Matlab的程序调用该tbl文件,即可观察波形。当然,利用Modelsim更好。-During Quartus simulation, waveform directly with their own simulation tools can not view the sine wave, Save the simulation data for the tbl format, using the
digital-filter-simulation
- 数字滤波器设计把整个设计方案用VHDL语言进行了描述并在Modelsim上仿真。-digital filter IIR Matlab VHDL Modelsim simulation
histogram-equalization-verilog
- 直方图均衡的Verilog实现 从Matlab读出图像为image.txt文件,经过Modelsim读入TXT文件进行直方图均衡处理,将输出结果再读出为image_he.txt文件,然后在Matlab观察直方图均衡增强效果。-The histogram equalization Verilog read from Matlab the image image.txt file after the Modelsim read into the TXT file, histogram equaliz
systolic--matrix-inversion
- DSP算法架构及设计,内容为基于systolic的上三角矩阵求逆电路的实现,里面有详尽的MATLAB/SIMULINK 仿真模型,及HDL代码和在modelsim中的仿真程序,非常不错的。-Architecture and design of DSP algorithms, based on systolic upper triangular matrix inverse circuit to achieve detailed MATLAB/SIMULINK model and the HDL
ofdm_integration
- 整合的OFDM调制解调方法,matlab文件,modelsim仿真-Integration OFDM modulation and demodulation method, matlab file, modelsim simulation
fir_lowpass
- 硬件语言实现数字低通滤波器,使用ise11.1和modelsim se6.5 仿真测试-Hardware language digital low pass filter, the use of simulation testing ise11.1 and modelsim se6.5
VLSI-Project-Median-filer
- FPGA和ASIC实现的图像中值滤波模块,各模块的仿真结果以及MATLAB,Modelsim联合仿真。这是中科大超大规模集成电路设计优化的final project。附有最终版的report和presention。-FPGA and ASIC implementation of image filtering modules, each module of the simulation results and MATLAB, Modelsim co-simulation. This is the
lisa-vhdl2va
- 通过modelsim仿真检测matlab生成滤波器效果。-Generate the filter through matlab and simulated by modelsim.
quartus和modelsim中使用mif和hex文件1
- quartus和modelsim中使用mif和hex文件1(fpga modelsim mif hex)