用VHDL实现了Matlab中MedFilt1函数3阶中值滤波。进行排序时没有用软件使用的排序法，而是通过简单的比较实现。-VHDL implementation using the Matlab function MedFilt1 of 3-order median filter. Sort of no use when the software used to sort the Law, but through a simple comparison of implementation.

FPGA和ASIC实现的图像中值滤波模块，各模块的仿真结果以及MATLAB,Modelsim联合仿真。这是中科大超大规模集成电路设计优化的final project。附有最终版的report和presention。-FPGA and ASIC implementation of image filtering modules, each module of the simulation results and MATLAB, Modelsim co-simulation. This is the

实现中值滤波的Verilog编程，并且还有matlab仿真验证-Verilog programming to achieve median filtering, and there matlab simulation

基于FPGA的图像中值滤波，在xilinx的FPGA上实现了算法，采用matlab的算法最终通过了验证。-FPGA-based image median filtering on xilinx FPGA implementation of the algorithm, using matlab algorithm finally passed validation.