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pipelined-mips-cpu
- 用verilog语言描述了MIPS的5级流水线。-Language described by verilog MIPS 5-stage pipeline.
PipeLine.tar Verilog实现MIPS五段流水线
- Verilog实现MIPS五段流水线，22条指令（基本算术、移位和load、store指令），模块化设计，含注释-Verilog realization of five-stage pipeline MIPS 22 instructions (basic arithmetic, shift, and load, store instructions), modular design, with annotations
cpu
- 5 stage pipeline CPU, verilog HDL code-5 stage pipeline CPU
CPU
- 32位5级流水线CPU设计指令系统、指令格式、寻址方式、寄存器结构、数据表示方式、存储器系统、运算器、控制器和流水线结构等-32bit pipeline CPU
DES_IP
- 有效的改进3-DES算法的执行速度，采用了多级流水线技术，设计了一种高速的硬件结构，使得原来需要48个时钟周期才能完成的运算，现在只需要一个时钟周期就可以完成。另外通过增加输入/输出的控制信号。使得该IP可以方便的集成到SOC中，大大缩短了SOC的设计周期。-Effective 3-DES algorithm to improve the implementation of speed, multi-stage pipeline technology, designed a high-speed
vhdl-pipeline-mips_latest.tar
- pipeline mips in vhdl
mips
- mips pipeline code.. copyright material for fr-mips pipeline code.. copyright material for free
mips
- pipeline mips processor
Pipelined-MIPS
- MIPS架构5级流水线设计，支持常用的整数指令。-5-stage pipeline MIPS architecture designed to support common integer instructions.
project
- s-stage MIPS pipeline with forwarding unit implemented in quartus ||
vhdl-pipeline-mips0
- MIPS CPU WITH PIPELINE procesador MIPS-FZA -- Autor: mahdi ahmadi -- Email: mahdi@fza.ir -- mahdifza@yahoo.com -- -- Version: 1.0
MIPSCPU_MultiCircle
- 流水线的一个循环源码设计，基于mips流水线的设计-Pipeline a loop source design, based on the design of the mips pipeline
MIPSCPU_Pipeline
- 流水线的设计，基于mips流水线的管道设计-Pipeline design, pipeline design based on mips pipeline
vhdl-pipeline-mips_latest
- pip-lined MIPS in vhdl
p21
- mips pipeline的源代码，很简洁，很适合新手使用。大学三年级的必修课。-mips pipeline source code, very simple, very suitable for beginners to use. University of grade three compulsory.
simple-pipeLine-CPU
- 简单的流水线CPU实现，基于MIPS指令集。-Simple pipelined CPU implementation, based on the MIPS instruction set.
Elham-Zahraei-Salehi_-Sina-Saharkhiz-(1)
- here it is a file which is consist of design of a MIPS pipeline in verilog, it also has test part an it work perfectly. the code is written in good way to understand it easily
PIPELINE
- （包含详细说明文档和简单汇编转机器码翻译器）五级流水线实现MIPS指令集（30条）含异常处理。结构采用多分支预测结构（基于历史的动态分支预测）-(Contains detailed documentation and compilation turn simple machine code translator) five pipelined MIPS instruction set (30) with exception handling. Structure using multi-bran
MIPS
- 5个stage的pipeline MIPS，支持着JUMP，BRANCH等跳转命令。-simple 5-stages MIPS structure which supports forwarding commands.
mips
- Verilog语言开发的基于mips指令集的流水线cpu，只支持部分指令-Verilog language-based development pipeline cpu mips instruction set support only part of the instruction