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FPGAprogram5
- 数控振荡器的频率控制字寄存器、相位控制字寄存器、累加器和加法器可以用VHDL语言描述，集成在一个模块中，提供VHDL源程序供大家学习和讨论。 -NC oscillator frequency control word register, phase control word register, and processing instruments used accumulator can be used VHDL descr iption, in an integrated modules
This VHDL code pertains to the DCO model
- code.doc C.1 DCO LEVEL 2 This VHDL code pertains to the DCO model descr iption in Section 6.5.5. The entity declaration of the level 2 DCO is between lines 18 and 39. The VHDL generics or elaboration-phase parameter constants are declared between
RomNCO
- 基于NCO的数字控制振荡器。带测试程序，输出12位的COS和SIN波形。-Based on the digital control oscillator NCO. With test procedures, the output 12 of the COS and the SIN waveform.
dpll
- 基于Verilog的数字锁相环。包括三个模块，数字鉴相器DPD、数字环路滤波器DLF、数控振荡器 DCO三部分构成-Verilog-based digital PLL. Consists of three modules, the digital phase detector DPD, digital loop filter DLF, digitally controlled oscillator DCO three parts
CordicNCO
- 基于CORDIC算法的，数字控制振荡器的设计。带测试程序，输入一个振荡频率，输出SIN和COS的波形！-Based on the CORDIC algorithm, the digital controlled oscillator design. With test procedures, enter a oscillation frequency, the output waveform SIN and COS!
DW8051_ALL
- 包中包括, DW8051完整的Verilog HDL代码 两本手册: DesignWare Library DW8051 MacroCell, Datasheet DesignWare DW8051 MacroCell Databook 三篇51论文: 基于IP 核的PSTN 短消息终端SoC 软硬件协同设计 Embedded TCP/ IP Chip Based on DW8051 Core 以8051为核的SOC中的万年历的设计 -DW8051 is desi
CORDIC
- 数字控制振荡器（NCO，numerical controlled oscillator）是软件无线电、直接数据频 率合成器（DDS，Direct digital synthesizer）、快速傅立叶变换（FFT，Fast Fourier Transform） 等的重要组成部分，同时也是决定其性能的主要因素之一，随着芯片集成度的提高、在信号 处理、数字通信领域、调制解调、变频调速、制导控制、电力电子等方面得到越来越广泛的 应用。-Digital controlled oscilla
counter
- 用VHDL语言实现的计时器，最大计时为24小时，计时精度为1ms，设有复位和暂停功能，使用的晶振频率为50Hz。-VHDL language implementation of the timer with a maximum time of 24 hours, timing accuracy of 1ms, with reset, and pause functions, using the crystal oscillator frequency is 50Hz.
VCO_WITH_PLL
- Voltage controlled oscillator with p-Voltage controlled oscillator with pll
ISE_lab16
- 使用VHDL语言设计数字钟。 数字钟由晶振、分频器、计时器、译码器、显示器等组成-Digital clock design using the VHDL language. Digital clock from the crystal oscillator, frequency divider, timer, decoder, display and other components
Fenpin
- 基于VHDL语言时钟晶振48Mhz的分频器的制作能够实现1HZ分频的时钟信号。-48Mhz clock oscillator based on VHDL language to achieve the production of crossover frequency of the clock signal 1HZ.
Jshuqi
- 基于VHDL原理图实现的计数器 时钟晶振为48MHZ -Schematic-based VHDL implementation of the counter clock oscillator is 48MHZ
code
- it is the collection of the modules involved inthe design of digital fm.the code coves the key components like numerically controlled oscillator, loop filter, fir filter ,phase detector along with the complete cicuit implementation of the digital fm
modifiedVCO_WITH_PLL
- voltage controlled oscillator using VHDL
FPGA-based-multi-Divider
- 分频器是指使输出信号频率为输入信号频率1/N的电子电路,N是分频系数。在许多电子设备中如电子钟、频率合成器等，需要各种不同频率的信号协同工作，常用的方法是以稳定度高的晶体振荡器为主振源，通过变换得到所需要的各种频率成分，分频器是一种主要变换手段。 本文当中，在分析研究和总结了分频技术的发展趋势的基础上，以实用、可靠、经济等设计原则为目标，介绍了基于FPGA的多种分频器的设计思路和实现方法。本设计采用EDA技术，以硬件描述语言VHDL为系统逻辑描述手段设计文件，在QuartusⅡ工具软件环境下
alpha_func
- This alphabet generating program in vhdl with various colors and models, i remodelled the oscillator to do this. maybe it will just for fun.-This is alphabet generating program in vhdl with various colors and models, i remodelled the oscillator to do