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  1. zhouligong-LPC17XX-example

    2下载:
  2. 周立功LPC17XX系列配套例程。包括AD,DAC,EINT.GPDMA.GPIO,I2C.IAP,PWM,QEI,RTC,SPI,SSP,TIMER,UART,储存器加速,掉电唤醒,数字输入,CAN,ETHERNET,USB,I2S例程。是学习 的很好例程,例程很全,很值。-Zhou, who LPC17XX series matching routines. Including AD, DAC, EINT.GPDMA.GPIO, I2C.IAP, PWM, QEI, RTC, SPI, SS
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2016-01-25
    • 文件大小:10853376
    • 提供者:夏波
  1. meanFilter

    0下载:
  2. This is a variable length window averaging filter that uses an MCP3002 ADC with SPI interface to sample an analog input, and has a PWM that can be run through a low-pass filter to produce an analog output. The design was simulated in Modelsim with no
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-03-24
    • 文件大小:16708
    • 提供者:Kelton
  1. vhdl

    0下载:
  2. 实验箱的蜂鸣器是交流蜂鸣器,在BZSP输入一定频率的脉冲时,蜂鸣器蜂鸣,改变输入频率可以改变蜂鸣器的响声。因此可以利用一个PWM来控制BZSP,通过改变PWM的频率来得到不同的声响,以此来播放音乐。-Experiment Box AC buzzer buzzer is in BZSP certain frequency pulse input, the buzzer beeps to change the input frequency can change the sound of the b
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-04
    • 文件大小:22016
    • 提供者:王记存
  1. adcpwm

    0下载:
  2. source code is an example of adc and pwm program in atmega 8535. This code will make the microcontroller converts each input of the ADC pin and make it into OCR0 value. This OCR0 value will affect the shape of the generated pwm signal. OC0 pin on POR
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-03-29
    • 文件大小:5490
    • 提供者:IPY
  1. servomat

    0下载:
  2. antidad_a EQU s0 talto EQU s1 Rename register sX with <name> tbajo EQU s2 indicador EQU s3 cantidad_b EQU S4 Define constant <name>, assign value name ROM output file generated by pBlazIDE assembler VHDL "ROM_form.vhd", "ser
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-05-06
    • 文件大小:1057345
    • 提供者:Jorge
  1. PWM-LED

    0下载:
  2. 根据输入电压改变pwm来调节LED输出光。-adjust PWM to dim LED according to input voltage.
  3. 所属分类:VHDL编程

    • 发布日期:2017-03-25
    • 文件大小:805
    • 提供者:
  1. PWM-design-Based-on-FPGA

    0下载:
  2. 本设计是基于FPGA控制的PWM信号输出系统,以EP3C5E144C8芯片为核心,通过参考信号和输入信号在计数器中的比较来实现占空比、频率可调的脉冲宽度调制信号-The design is FPGA-based control of the PWM signal output system, to EP3C5E144C8 chip as the core, to achieve adjustable duty cycle, frequency, pulse width modulation si
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-11-15
    • 文件大小:6710438
    • 提供者:席晓明
  1. servo

    1下载:
  2. Verilog编写的辉盛9g舵机控制程序,clk:25MHz,输入角度(0~180),输出PWM,直接连到舵机引脚上即可使用-Verilog prepared Fraser 9g servo control procedures, clk: 25MHz, input angle (0 to 180), the output PWM, directly connected to the steering pin can be used
  3. 所属分类:VHDL编程

    • 发布日期:2014-03-13
    • 文件大小:551
    • 提供者:张立嘉
  1. PWM

    0下载:
  2. 此程序利用FPGA芯片的内部时钟,根据输入信号,产生占空比可调的方波信号。-This program uses the FPGA chip s internal clock, according to the input signal to generate variable duty cycle square wave signal.
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-11
    • 文件大小:573
    • 提供者:lmy
  1. PWM

    1下载:
  2. FPGA根据输入的电压参考值产生六路PWM波-FPGA according to the voltage reference input values to generate six PWM wave
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-05-09
    • 文件大小:1623514
    • 提供者:张宇
  1. pwm

    0下载:
  2. 一个宽度脉冲调制pwm的模板,因为是学习使用的,增加了数据输入以便在开发板的led灯中观看实验现象,输入数据越大led的亮度越大-A pulse width modulation pwm template, because it is learning to use, increasing the data input for viewing experimental phenomena in the development board led lamp, the greater the gre
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-05-12
    • 文件大小:3026260
    • 提供者:邓智浩
  1. refrigerator

    0下载:
  2. 基于DE2 FPGA开发板的电冰箱控制系统源代码。Quartus 2开发环境。主要功能有检查系统输入,PWM输出,控制LED等。-Based on DE2 FPGA development board refrigerator control system source code. Quartus 2 development environment. The main function is to check the system input, PWM output, control LED a
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-12-15
    • 文件大小:874496
    • 提供者:wu
  1. Nexys4FFTDemo-master

    0下载:
  2. A simple Verilog example of a 4096pt FFT on analog input from a Nexys 4 XADC. The input is sampled at 1MSPS, oversampled to produce 14-bit samples at 62.5kHz, then sent to the FFT processing modules and passed through to PWM Audio out. The FFT output
  3. 所属分类:VHDL/FPGA/Verilog

    • 发布日期:2017-12-19
    • 文件大小:181248
    • 提供者:jason912
  1. PWM

    1下载:
  2. 利用Verilog语言设计一个PWM控制器,实现:控制器输入时钟1MHz;控制器输出脉冲周期1kHz,脉宽最小调节步长0.1%。(The Verilog language is used to design a PWM controller, which is realized: the controller input clock 1MHz; the controller output pulse cycle 1kHz, and the pulse width minimum adjustme
  3. 所属分类:VHDL/FPGA/Verilog

    • 发布日期:2018-01-06
    • 文件大小:62464
    • 提供者:jcg17
  1. deadzone

    0下载:
  2. 代码功能是实现脉冲信号的死区控制。根据输入脉冲实现10us的死区,避免IGBT直通。(The code function is to realize the dead zone control of the pulse signal. The dead zone of 10us is realized according to the input pulse, and the direct connection of IGBT is avoided.)
  3. 所属分类:VHDL/FPGA/Verilog

    • 发布日期:2018-04-29
    • 文件大小:1024
    • 提供者:FollowSky
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