Two simple Quadrature decoder and Counter build in a XILINX XC9536 CPLD. This Core is coded in Verilog and contains the compete Project file and the fitted quad.jed File. The Pinout is descr ipted in the Constrained file quad.ucf. To use them, y

利用D触发器实现的2倍频正交解码，稳定性高，相对4倍频较简单-The use of D flip-flop to achieve two octave quadrature decoder, high stability, relatively simple four octave