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maxshiyan
- 大学vhdl语言实验大全,基于max-plus2平台,内有8-3译码器,8位加法器,数字钟，数码显示，74ls138，8，4位计数器，d，rs触发器，加法器，交通灯等，此原码基于长江大学可编程器件实验箱,如要运行在其他平台上需要重新定义管脚-University VHDL language experiment Daquan, based on the max-plus2 platform within 8-3 decoder, 8 Adder, digital clock, digital d
rs-codec-8-16
- RS[255,223]纠错码verilog源码，包含编码和解码模块，以及testbench等。-Verilog source code for RS[255,223] encoder and decoder, with testbench included.
verilogRS
- 该文件为基于fpga的RS（204.188）译码器的verilong源代码，使用的Quartus II的开发环境，已经通过编译，需要者可以自己下载在编译简历工程使用-The document is based on fpga' s RS (204.188) decoder verilong source code, use the Quartus II development environment, has been compiled by the need to download th
RS
- RS译码器的设计，使用RS码设计的译码器-RS decoder design, the use of RS code decoder design
RS
- RS译码器的设计源程序--verilog HDL实现-Design of the RS decoder source code-- Verilog HDL
(255_223)-RS-decoder
- 使用VHDL实现（255,233）的RS硬件译码器，详细地介绍了(255，223)RS码硬件译码器的实现流程，并且分析了影响处理速率提高的瓶颈因素，采用RiBM算法实现译码-Use VHDL (255,233) RS hardware decoder, a detailed descr iption of the (255,223) RS code hardware decoder implementation process, and analyze the bottleneck factor