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heartbeat
- 用VHDL编译的源代码，模拟心脏跳动，解压后直接用Quartus打开project即可，不好意思刚才第一个那个模拟心脏跳动（heartbeat）的源程序发错了，请删除，-Compiled with VHDL source code to simulate the beating heart, after extracting the direct use of Quartus can open the project, I am sorry but the first one that simu
P8051
- This a FREE tool chain which compiles C codes into 8051 binary code, converts the binary to RTL ROM, and simulate in Modelsim. SDCC is the compiler. Example compilation: cd compile sdcc --iram-size 0x80 --xram-size 0x800 t8051.c RE
svc_timer33ms
- Verilog 下脉冲发生器的源代码，可用于模拟三相交流电过零点，主要用于调试一些类似SVC（无功补偿）控制器的一些算法-Pulse generator under the Verilog source code, can be used to simulate three-phase alternating current zero-crossing point, mainly for debugging similar SVC (reactive power compensation) co
Vhdl1
- Top Level VHDL Code -- simulate the relatively slow progress of an elevator car by dividing the -- clock down by an outrageously high number and scanning the car registers for -- an elevator s next -- (normally the signals used below wo
fft_gen
- FFT vhdl generic: I m new to vhdl, and I tried to use xilinx fft core, but when I try to simulate it in test bench using ise simulator, I get zero results. here is what I do: 1- from core generator I choose fft core and create .vhd & .vho &
adder
- This the adder VHDL code, it contains input and output fild, also simulate file-adder
spreadingcommunicatinon
- spearding progect by vhdl code simulate
noise
- 随机噪声产生代码。所输出的随机噪声可以用于模拟信道中的加性噪声。-Random noise generated code. The output of the random noise can be used to simulate the channel additive noise.
SpiMaster
- This a verilog code for SPI Master testbench is also provided spi_top.v Xilinx ISE or Icarus verilog to compile and simulate-This is a verilog code for SPI Master testbench is also provided spi_top.v Xilinx ISE or Icarus verilog to compile an
VHDLshixianCPU2
- vhdl实现cpu用verilog写的8位CPU源码，通过汇编语言可以实现加减乘左移右移等运算。并通过ASC流程可以模拟出其内部电路结构。代码，截图，readme在文件夹中-With 8-bit CPU to write verilog source code, assembly language can be achieved through the addition, subtraction and other operations right left. ASC process throu
GPIOsimulateUART
- 此代码是用8051普通的GPIO口来模拟串口-This code is to use the GPIO port 8051 to simulate an ordinary serial port
AssignmentP6
- 1. For the VHDL model given below (Code List One), compare the FIFOs implementations on CPLD and FPGA. (1) Synthesize and verify (simulate) the VHDL design of the FIFOs (2) For CPLD implementation (fit) of the FIFOs, how many MCs (macrocells)
AssignmentP4
- Assignment 4: 1. Analyze and simulate the following code lists (code1 and code 2) with the same input signals shown below by presenting POW and OL. If the data type of “a, b, c, d, u, v, w, x, y, z” is declared as std_logic, what will the simulatio
The--VHDL-code-of-I2C
- 该程序采用延时接收比较来实现仲裁的方法，使不具有I2C接口的普通微控制器（MCU）能够实现模拟I2C总线的多主通信。-This program is to realize the delay receiving the arbitration method, do not have the I2C interface of ordinary micro controller (MCU) can simulate the I2C bus more than the main communicati
Hamming32
- It has a simple verilog code to calculate 32 bit hamming distance and a test bench to simulate.
nios2PtfcardPvga
- 使用nios的io管脚模拟spi时序对tf卡进行数据读写，同时附带一个简单的用verilog写的在vga显示器上刷屏的代码-Use the io pin of nios to simulate the timing of spi to read&write date from&to tf card, and comes with a simple code written by verilog to refresh the vga monitor.
fifo
- VHDL code for DATA PATH for performing A=A+3 and A=B+C TO DESIGN AND SIMULATE DATA PATH FOR PERFORMING A=A+3 AND A=B+C USING ONLY ONE ADDER.
COMB
- We use port map statement to achieve the structural model (components instantiations). The following example shows how to write the program to incorporate multiple components in the design of a more complex circuit. In order to simulate the design, a
fpu_double
- The Verilog version of the code is in folder “fpu_double”, and the VHDL version is in folder “double_fpu”. There is a readme file in each folder, and a testbench file to simulate each core. These cores are designed to meet the IEEE 754 standard f
8b10b_encdec_latest.tar
- this a vhdl code to simulate 8b/10b encoder and decoder with a test bench-this is a vhdl code to simulate 8b/10b encoder and decoder with a test bench