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SPI_Master_module
- 利用VHDL语言编写的SPI主机模块,采用内部自环回已经经过测试,发送接收数据正常,里面有modelsim工程,可以验证下仿真波形-SPI host module using VHDL language, has passed internal self-loopback test, sending and receiving data normally modelsim project, which can be verified under simulation waveforms