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spi
- VHDL实现SPI功能源代码 -- The SPI bus is a 3 wire bus that in effect links a serial shift -- register between the \"master\" and the \"slave\". Typically both the -- master and slave have an 8 bit shift register so the combined -- register is 16 bits
SPI_collect
- 有关SPI的vhdl实现。包括SPI官方协议，几篇开发时用到的论文，附加了中文注释的SPI IPcore，还有一个经过简化的master mode的SPI实现的vhdl代码
FPGASPI
- 用FPGA实现主SPI程序,包含开发工程、测试文件和源文件代码-fpga design the SPI code
spi_master_control
- VHDL SPI 控制器FPGA官网提供-VHDL SPI controller FPGA to provide official website
spi_master
- SPI接口的实现以及对外设的读写操作，其中包扩了几种工作方式，同时可以读取外设的版本号，传输速率可以达到2Mbps-SPI interface implementation, as well as read and write operations on the peripheral, which extended several work packages at the same time can read the version number of peripherals, transfer
l1ghVhVI
- The VSPI core implements an SPI interface compatible with the many -- serial EEPROMs, and microcontrollers. The VSPI core is typically used -- as an SPI master, but it can be configured as an SPI slave as well.
SpiMaster
- This a verilog code for SPI Master testbench is also provided spi_top.v Xilinx ISE or Icarus verilog to compile and simulate-This is a verilog code for SPI Master testbench is also provided spi_top.v Xilinx ISE or Icarus verilog to compile an
SimpleCode
- SPI Master Driver with VHDL
spi_master
- 用VHDL编写的一个SPI主机程序，SPI模块采用最常用的模式0方式（即CPOL=0,CPHA=0）通信。文件内含测试文档，已在Modelsim6.5上测试通过，可在FPGA上直接调用。-A SPI Master code edited by VHDL language,the SPI modul use 0 MODE(i.e CPOL=0,CPHA=0)to communicate with the SPI Slave.and there is a testbench in the file
xapp386
- This document details the VHDL implementation of a Serial Peripheral Interface (SPI) master in a Xilinx® CoolRunner™ -II CPLD. CoolRunner-II CPLDs are the lowest power CPLDs available, making this the perfect target device for an SPI Mas
xapp348
- This document details the VHDL implementation of a Serial Peripheral Interface (SPI) master in a Xilinx CoolRunner™ XPLA3 CPLD.-This document details the VHDL implementation of a Serial Peripheral Interface (SPI) master in a Xilinx CoolRunne
spi_final_presentation
- Implement SPI Master and SPI Slave cores (VHDL) Implement Master and Slave hosts (VHDL) Verify the entire design (SystemVerilog)
SPI-Master-Core-DAC-ADC-spartan
- SPI Master Core for spartan (ADC, DAC) vhdl code
SPI_MASTER
- VHDL实现的SPI Master 采用标准状态机，已完成实际验证-VHDL implementation of SPI Master standard state machine has completed the actual verification
SPI-master-P-tb
- SPI master VHDL realisation Also contains TestBench
simple_spi_latest.tar
- 基于vhdl的spi主从模式的程序，实现简单的SPI收发，对于实际使用学习是个比较好的例子！-VHDL SPI master-slave mode based on the procedures, the realization of a simple SPI transceiver for practical use, is a good example of learning!
spi_master_module
- Simple VHDL SPI-module core source code (only spi-master)
spi_mem_programmer-master
- spi_mem_programmer A simple verilog module for programming (Q)SPI flash memories
verilog_spi-master
- verilog_spi A simple demo SPI interface implemented in verilog
spiVerilog-master
- spiVerilog A Verilog SPI module