搜索资源列表
PL_FSK
- 数字通信系统通信系统调制解调（PL_FSK）VHDL建模，包括发送和接受模块-Digital Communication System Communication System modulation and demodulation (PL_FSK) VHDL modeling, including sending and receiving modules
a_block_with_several_functions_with_Verilog_HDL.ra
- Verilog是广泛应用的硬件描述语言，可以用在硬件设计流程的建模、综合和模拟等多个阶段。随着硬件设计规模的不断扩大，应用硬件描述语言进行描述的CPLD结构，成为设计专用集成电路和其他集成电路的主流。通过应用Verilog HDL对多功能电子钟的设计，达到对Verilog HDL的理解，同时对CPLD器件进行简要了解。 本文的研究内容包括: 对Altera公司Flex 10K系列的EPF10K 10简要介绍，Altera公司软件Max+plusⅡ简要介绍和应用Verilog HDL对多功能
shuzitongxinxitongjianmo02
- 基于CPLD_FPGA的数字通信系统建模与设计，本学习资料共分为4个部分，此为第一部分，供对数字通信系统建模和设计有兴趣的朋友学习参考。-CPLD_FPGA based on the digital communication system modeling and design, the learning materials is divided into four parts, this is the first part of the digital communication syste
shuzitongxinxitongjianmo04
- 基于CPLD_FPGA的数字通信系统建模与设计，本学习资料共分为4个部分，此为第四部分，供对数字通信系统建模和设计有兴趣的朋友学习参考。-CPLD_FPGA based on the digital communication system modeling and design, the learning materials is divided into four parts, this is the fourth part of the digital communication syst
QAM
- VHDL-AMS Behavioral Modeling and Simulation of M-QAM transceiver system
vhdl-tutorial
- VHDL Tutorial, it describes the modeling language VHDL. VHDL includes facilities for describing logical structure and function of digital systems at a number of levels of abstraction, from system level down to the gate level. It is intended, am
TIMEFACEDETECTIONANDLIPFEATUREEXTRACTIONUSINGFPGA
- Abstract—This paper proposes a new technique for face detection and lip feature extraction. A real-time field-programmable gate array (FPGA) implementation of the two proposed techniques is also presented. Face detection is based on a naive Bay
veriloghdl
- Verilog HDL是一种硬件描述语言，用于从算法级、门级到开关级的多种抽象设计层次的 数字系统建模。被建模的数字系统对象的复杂性可以介于简单的门和完整的电子数字系统之间。数字系统能够按层次描述，并可在相同描述中显式地进行时序建模。-Verilog HDL is a hardware descr iption language, used from the algorithm level, gate-level to switch level design of a variety of
verilog_tutorial
- Chapter 1 Introduction Chapter 2 History of Verilog Chapter 3 Design and Tool Flow Chapter 4 My First Program in Verilog Chapter 5 Verilog HDL Syntax and Semantics Chapter 6 Gate Level Modeling Chapter 7 User Defined Primitives Chapter
verilog
- verilog学习课件。介绍了verilog硬件描述语言的基础知识，包括语言的基本内容和基本结构，以及利用该语言在各种层次上对数字系统的建模方法。-verilog learning courseware. Introduced the verilog hardware descr iption language basics, including basic elements of language and basic structure, and the use of the language
practical_design_verification
- Improve design efficiency and reduce costs with this practical guide to formal and simulation-based functional verification. Giving you a theoretical and practical understanding of the key issues involved, expert authors explain both formal tec
ExtremeEDA100-SystemC_UT_Intro
- ExtremeEDA的系统建模与systemC语言教程讲义，内容包括系统建模概念，systemC语法以及应用实例-System modeling and systemC ExtremeEDA language tutorial handouts, including system modeling concept, systemC syntax and examples
wu
- 通信原理基于VHDL的课程设计，基于CPLD_FPGA的数字通信系统建模与设计（通信课设参考书）-VHDL-based communication principle of curriculum design, digital communication system based on CPLD_FPGA Modeling and Design (Communications course design reference)
CPLD_FPGA
- 基于CPLD/FPGA的数字通信系统建模与设计，里面讲述了通信系统的VHDL建模和各种基本电路的建模与设计，在通信原理课程设计中一般会用到！-Based on CPLD/FPGA Digital Communication System Modeling and Design, which describes VHDL modeling of communication systems and a variety of basic circuit modeling and design, pri
Example-4-17
- 学习异步复位、同步释放电路建模的方法。异步复位、同步释放的具体设计方法很多，关键是如何保证同步地释放复位信号。本例的设计方法是在复位信号释放时，用系统时钟采样，然后将复位信号送到寄存器的异步复位端。-Learning asynchronous reset, synchronous release of circuit modeling approach. Asynchronous reset, synchronous release of many of the specific design,
Digital-baseband-system-
- 是基带方面的权威资料，好好参考会明白基带传输的原理和意义的-Digital baseband system modeling and design
beep_interface
- 这些代码为 对于基本的FPGA使用模块beep进行了例化 在工程 系统级建模时只需要直接调用就好了-The code for the basic FPGA using the module beep instantiated only need to be called directly in the engineering system-level modeling like
HDB3
- 按照要求对“数字基带信号HDB3译码器设计与建模”进行逻辑分析，了解HDB3译码器译码原理，了解各模块电路的逻辑功能，设计通信系统框图，画出实现电路原理图，编写VHDL语言程序，上机调试、仿真，记录实验结果波形，对实验结果进行分析。(In accordance with the requirements of the logical analysis of the design and modeling of the digital baseband signal HDB3 decoder, H