搜索资源列表
DDR_SDRAM_controller
- DDR SDRAM控制器的VHDL源代码，含详细设计文档。 The DDR, DCM, and SelectI/O™ features in the Virtex™ -II architecture make it the perfect choice for implementing a controller of a Double Data Rate (DDR) SDRAM. The Digital Clock Manager (DCM) provides t
test
- wARM体系结构的VHDL设计，研究ARM体系设计很有用-WARM VHDL architecture design, research useful ARM System Design
microprocessor
- 一个微处理器的Verilog代码，根据英文书籍《数字设计与架构》中的例子而写，能够运行MIPS指令，能正确执行跳转指令。通过modelsim仿真，含测试代码。-Verilog code for a microprocessor, according to the English book " Digital Design and Architecture" was written in the example, to run MIPS instructions to jump
simpleCPUdesign
- 本文档介绍了一个简单的单周期CPU，和流水线CPU的实现过程。 这是我们完成伯克利大学EECS系计算机系统结构课程的实验文档，实验信息见http://www-inst.eecs.berkeley.edu/~cs152/fa05/-This document describes a simple single-cycle CPU, and CPU pipeline implementation process. This is the complete Berkeley EECS Departme
Bist_codings
- In this paper, we have explained the purpose of FPGA testing. A built-in-self-test (BIST) is one type of testing. This test is performed internally to find any faults within a FPGA chip. This paper explains why testing is important to FPGAs. It also
bist(1)
- In this paper, we have explained the purpose of FPGA testing. A built-in-self-test (BIST) is one type of testing. This test is performed internally to find any faults within a FPGA chip. This paper explains why testing is important to FPGAs. It also
hierarchical-code
- Abstract—This paper presents a highly effective compactor architecture for processing test responses with a high percentage of x-values. The key component is a hierarchical configurable masking register, which allows the compactor to dynamically ad
handbook
- Abstract—This paper presents a Viterbi-based test compression algorithm/architecture that provides high encoding efficiency and scalability with respect to the number of test channels. The proposed scheme finds a set of compressed test vectors
ARM JTAG Debug
- 这篇文章主要介绍 ARM JTAG 调试的基本原理。 基本的内容包括了 TAP (TEST ACCESS PORT) 和 BOUNDARY-SCAN ARCHITECTURE 的介绍， 在此基础上， 结合 ARM7TDMI 详细介绍了的 JTAG 调试原理。(OPEN-JTAG Development Group.)
bist 2017 paper
- A new low-power (LP) scan-based built-in selftest (BIST) technique is proposed based on weighted pseudorandom test pattern generation and reseeding. A new LP scan architecture is proposed, which supports both pseudorandom testing and deterministi