使用该VHDL在仿真软件中实现RSC(递归系统卷积)码的编码以及解码硬件仿真-use of the VHDL simulation software in achieving RSC (recursive convolution system) code encoding and decoding hardware simulation

采用vhdl语言编写的卷积编码（2.1.7），通过调试可直接下载使用-Convolution using vhdl language code (2.1.7) can be directly downloaded through the use of debugging