搜索资源列表
userbscan
- xilinx FPGA上使用jtag接口作为用户IO的源码。支持任意位宽度。-Xilinx FPGAs use JTAG interface as user IO source. Support for arbitrary bit width.
i2cjiekouchengxu
- 这是一个IIC的接口程序，是夏宇闻编的书《verilog 数字系统设计教程》的IIC的源码，很通俗易懂-IIC interface procedures, Xia Wen is the book series "verilog Digital System Design Guide," the IIC the source, very user-friendly
I2C_Slave
- I2C从设备（Slave） Verilog 代码、设计文档和使用文档，简单、适用：很方便修改工作频率，自定义寄存器接口。-I2C slave (Slave) Verilog code, design documents and user guide, simply to apply: the frequency of easy modification, customized register interface.
mcb_read_write
- 赛灵思 DDR2 用户接口程序 原创。希望对各位有用。-Xilinx DDR2 original user interface program. You want to be useful.
E8051_256
- This contains the main-level VHDL files required for an example complete, ready-to-use, FPGA/ASIC 8051 microcontroller. The corresponding main schematic can be found in the Schematics folder, and a technical descr iption of the e8051 core inter
miniuart2
- 用ＶＨＤＬ在CPLD/FPGA上实现与PC机的RS232通信-This UART (Universal Asynchronous Receiver Transmitter) is designed to make an interface between a RS232 line and a wishbone bus, or a microcontroller, or an IP core. It works fine connected to the serial port of a
sp601_MIG_rdf0005_12.2
- spartan—6fpga 用mig生成ddr2接口的ip核，用户可以直接调用此ip控制ddr2-spartan-6fpga generated by mig ddr2 interface ip core, the user can call this ip control ddr2
XUPV2P_Base_System_Builder
- The Base System Builder (BSB) wizard is a software tool that help users quickly build a working system targeted at a specific development board. Based on the user’ s board selection, BSB will offer the user a number of options for creating
FPGA-imitate-RS232
- FPGA仿RS232通讯接口，因FPGA一般无串口，故可设置用户I/O模仿串口功能-RS232 communication interface FPGA imitation, because usually no serial FPGA, it can set user I/O port features mimic
clock
- 使用Quartus II图形界面连接的数字电子时钟设计，内含报告word文档-Using the Quartus II graphical user interface connected to digital electronic clock design, word document containing the report
vga_lcd_latest.tar
- vga lcd 控制器 24位VGA控制，支持12位DVI协议-This embedded VGA core capable of driving CRT and LCD displays. It supports user programmable resolutions and video timings, which are limited only by the available WISHBONE bandwidth. Making it compatible with almost
XAPP454
- Spartan3a MIG user interface
Based-on-the-FPGA-VGA-display
- VGA(视频图形阵列)作为一种标准的显示接口得到广泛的应用。利用FPGA芯片和EDA设计方法，可以因地制宜，根据用户的特定需要，设计出针对性强的VGA显示控制器。-VGA ( Video Graphics Array ) as a standard display interface is widely used. Using FPGA chips and EDA design method, can suit one s measures to local conditions, accord
ddr_sdr_latest[1].tar
- ddr sdram 控制器的接口，为工业标准化存储设备提供简单的接口-The DDR SDRAM Controller provides the user with a simplified interface to industry standard memory devices. Using this controller makes accesses to DDR SDRAM devices as simple as possible.
VGA_CCD531
- 本文围绕一个包含Nios II软核处理器的可编程片上系统展开数码相机的样机设计。论文首先对样机所要达到的整体功能进行了规划，接下来并行开展了软硬件设计。在硬件方面，充分利用了所使用平台提供的SD卡插槽、键盘、数码管、SRAM等各种硬件资源，并用Verilog HDL硬件描述语言设计了样机系统所需要的VGA接口控制器、CMOS图像传感器接口控制器以及VGA显示存储器；在软件方面，本文基于Nios II软核处理器用C语言实现了SD卡的驱动、FAT文件系统的移植、VGA显视器的驱动以及BMP图片文件的
hill
- 本文介绍基于NiosII系统的家庭健康专家的设计。该设备定位于医疗保健领域内的家用电子产品，为家庭各个成员提供健康测量、健康教育、科学锻炼与数据综合等功能。设备采用了uC/OSII实时操作系统，可灵活的自定义外设，实现了大容量的数据存储，友好的用户界面和可靠的系统控制。-This article describes the design based on NiosII system of family health experts. The positioning of the device i
ml605_PCIe_Gen1_x8_rdf0008_13.4_c
- 该压缩文件为一个pcie接口设计源程序，源程序包含一个8通道gen1的pcie IP CORE和相应的用户接口程序，烧到开发板ml605中测试通过。 -The compressed file is a pcie interface design source code, source code contains an 8-channel gen1 of pcie IP CORE and the corresponding user interface program, burn developm
DBounce
- Using mechanical switches for a user interface is a ubiquitous practice. However, when these switches are actuated, the contacts often rebound, or bounce, off one another before settling into a stable state. Several methods exist to deal with this te
USRP-PID-Controller-clean
- PID feedback controller project for USRP1 boards (FPGA with a convenient analog front manufactured by ettus research). Implements a bitstream as well as python-based user interface.
modelsim se 10.1a crack
- Mentor公司的ModelSim是业界最优秀的HDL语言仿真软件，它能提供友好的仿真环境，是业界唯一的单内核支持VHDL和Verilog混合仿真的仿真器。它采用直接优化的编译技术、Tcl/Tk技术、和单一内核仿真技术，编译仿真速度快，编译的代码与平台无关，便于保护IP核，个性化的图形界面和用户接口，为用户加快调错提供强有力的手段，是FPGA/ASIC设计的首选仿真软件。(Mentor's ModelSim, the industry's best HDL language simulation