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FPGA读写控制sram
- 拨码开关控制读写，按键控制地址加，读出数据由数码管显示，直观展现了程序是否正确。
FPGA-verilog-交通灯
- 采用verilog编写的代码，用FPGA实现交通灯控制，包含有数码管显示控制，倒计时控制，状态机等，是练习Verilog代码编写的一个很好的实例！
shuma.rar
- 数码管动态显示程序，verilog的，已经调试成功,verilog
shumaguan.rar
- 用CPLD驱动数码管，实现从0000计到9999，数码管是用动态显示，程序用VERILOG完成的,CPLD drives with digital control, of from 0000 to 9999, digital control is a dynamic display, the program completed with VERILOG
fsmled
- verilog语言, 状态机实现数码管显示 -This uses verilog language to make state machine realization of digital control
TLC549
- verilog TLC549AD采样程序 ，速度200K，在LED和数码管上显-verilog TLC549AD sampling procedures, the speed of 200K, in the LED and digital tube significantly
DF2C8_04_BEEP
- verilog实现蜂鸣器自动演奏一首乐曲，同时数码管显示当前演奏的简谱音符 符号。-verilog achieve buzzer automatically play a piece of music, and digital display notes the current performance of the musical notation symbols.
eda
- 利用ATMEL公司的QUETUSii软件编写的verilog语言程序，实现一个带复位、调整时间功能的电子钟，以数码管显示时间，调整时间时调整位闪烁-ATMEL Corporation QUETUSii using software written in verilog language program, the realization of a zone reset, adjust the time function of the electronic clock to digital disp
verilog
- verilog实现的数字频率计8位数码管输出显示同时矩形波分档输出-verilog implementation of digital frequency meter
jiaotongdeng
- 1). 用红、绿、黄三色发光二极管作信号灯。主干道为东西向，有红、绿、黄三个灯；支干道为南北向，也有红、绿、黄三个灯。红灯亮禁止通行；绿灯亮允许通行；黄灯亮则给行驶中的车辆有时间停靠到禁行线之外。 2).由于主干道车辆较多而支干道车辆较少，所以主干道绿灯时间较长。当主干道允许通行亮绿灯时，支干道亮红灯。而支干道允许通行亮绿灯时，主干道亮红灯，两者交替重复。主干道每次放行50秒，支干道每次放行30秒。 在每次由亮绿灯变成亮红灯的转换过程中间，需要亮5秒的黄灯作为过渡，以使行驶中的车辆有时间
Mars_EP1C6F_Interface_demo(Verilog)
- FPGA开发板配套Verilog代码。芯片为Mars EP1C6F。一些接口通信的源码。包括7段数码管、I2C通讯等。-FPGA development board supporting Verilog code. Chips for the Mars EP1C6F. Some of the source interface. Including 7 digital tube, I2C communications.
i2c_AT24C04_Verilog
- 用Verilog HDL语言编写的AT24C04程序，并用数码管显示，已经过测试，很好用-With the Verilog HDL language of the AT24C04 procedures and use digital tube display, has been tested, very good to use--
verilog
- 通过I2C接口读写EEPROM 在本项目中，我们利用Verilog HDL实现了部分I2C总线功能，并能够通过该总线对AT24C02进行读写操作。为了便于观察读写eeprom的结果，我们将读写的数据同时显示在七段数码管上，并设定读写的数据从0到255不断循环，这样就可以方便进行比较。 -Through the I2C interface to read and write EEPROM in this project, we use Verilog HDL to achieve some o
seg
- 数码管显示（verilog） 自己写的 在数码管上显示01234567 动态显示-Digital LED display (verilog) himself wrote in the digital tube display 01234567 dynamic display
FPGA-verilog
- 用Verilog语言编写的一些简单的FPGA入门实验，用ALTERA DE2开发板和Quartus_II软件开发环境。包括：流水灯实验、数码管显示实验-With Verilog language preparation some simple introduction experiment, with FPGA ALTERA DE2 development board and Quartus_II software development environment. Include water l
pinlvji
- 自己编的一个频率计，verilog语言写的，用数码管显示方波的频率，测量量程是0.1hz~9999999hz，测方波的稳定性极高。-Their series a frequency counter, verilog language written with the digital display of the square wave frequency, measurement range is 0.1hz ~ 9999999hz, high stability of the square w
my6
- fpga verilog程序，实现诸多模块功能，包括，数码管显示，与ad，da通信，与mcu通信，以便通过mcu将高速ad值显示在lcd显示器上。-fpga verilog program to achieve a number of modules, including, digital display, with the ad, da communication, communication with mcu, mcu high-speed through the ad to the val
SMG
- 实现将BCD码动态扫描显示在数码管上--verilog(The realization of dynamic scanning BCD code displayed on the digital tube --verilog)
Exp_5
- 数码管动态显示，可以将输入的按键值显示在数码管上。(Dynamic display of digital tube)
teacher_uart
- 由verilog编写的uart收发模块，能够在串口助手发送字符，并在数码管上显示，开发板为basys3 内置约束文件(The UART transceiver module written by Verilog can send characters to serial assistant and display them on the digital tube. the development board is built-in constraint file of basys3)