搜索资源列表
D触发器的设计
- D触发器的设计 主要用在时序电路中。 所用语言为Verilog HDL.-D flip-flop with the main design of the timing circuit. The language used for Verilog HDL.
verilog
- verilog原理与应用 作者：Michael D. Ciletti
A/D转换芯片TLC2543的verilog编程
- A/D转换芯片TLC2543的verilog编程，根据TLC5243的datasheet编写，程序简单，结构清晰，可以借鉴应用-A/D converter chip TLC2543 the verilog programming
TRDB_DC2
- DE1/DE2CCD摄像头Verilog源代码。-DE1/DE2CCD camera Verilog source code.
max197
- verilog编写的状态机控制A/D芯片MAX197正常工作-use verilog write the state machine which is used to meke the A/D chip working!
AD9708
- AD9708是高速AD转换芯片，采用VHDL实现10MSPS高速AD数据采集-AD9708 is high speed a/d conversion chip,10MSPS,using VHDL
DCM
- xilinx SP605开发板的DCM模块验证程序，coreGen工具生成DCM核，由DCM完成时钟分频、倍频、移相等操作-xilinx SP605 development board DCM module validation program, coreGen tool to generate nuclear DCM, completed by the DCM clock divider, frequency, and shift operations equal
2DImageFilterByVHDL
- 用VHDL语言编程实现2维图像的滤波算法，简单精辟-VHDL programming language used to achieve 2-D image filtering algorithm, simple brilliant
dff
- 用vhdl编写的D触发器，锁存器等，不需帐号就可自由下载此源码-VHDL prepared using D flip-flops, latches and so on, no account can be a free download this source
TLC5510_VHDL
- 基于VHDL语言，实现对高速A/D器件TLC5510控制-Based on the VHDL language, to achieve high-speed A/D device control TLC5510
shifter
- 移位运算器SHIFTER 使用Verilog HDL 语言编写，其输入输出端分别与键盘/显示器LED 连接。移位运算器是时序电路，在J钟信号到来时状态产生变化， CLK 为其时钟脉冲。由S0、S1 、M 控制移位运算的功能状态，具有数据装入、数据保持、循环右移、带进位循环右移，循环左移、带进位循环左移等功能。 CLK 是时钟脉冲输入，通过键5 产生高低电平M 控制工作模式， M=l 时带进位循环移位，由键8 控制CO 为允许带进位移位输入，由键7 控制:S 控制移位模式0-3 ，由键6 控制
analogue-digi-ana-converter
- design and implementation of a format conversion system on the Altera NIOS board(QUARTUS) which reads an analogue input, converts it into digital data, and then does the reverse conversion back into analogue format. This will be done by taking an ana
DDS
- 基于Verilog的dds设计，已经经过调试，可直接使用-Dds of Verilog-based design, has been testing can be used directly
DAC_TLV5616
- tlv5614的驱动程序，用verilog语言编写的，fpga芯片为altera公司的ep2c35。 调试成功放心使用-tlv5614 driver, using verilog language written in, fpga chips altera company ep2c35. Assured the success of the use of debugging
dff_clk
- 简单的D触发器的Verilog描述及，仿真波形-A simple D flip-flop in Verilog descr iption and simulation waveforms
74hc74
- 带使能和清零端的D触发器，Verilog实现，有实验说明文档。-With a clear end to enable and D flip-flop, Verilog implementation, there is experimental documentation.
D_latch
- actel fpga Verilog D锁存器-actel fpga Verilog D latch
Advanced-Digital-Design-with-the-Verilog-HDL-CODE.
- 《Verilog HDL高级数字系统设计》（Michael D. Ciletti著） Verilog HDL源代码-" Verilog HDL Advanced Digital System Design" (Michael D. Ciletti a) Verilog HDL source code
D
- FPGA VERILOG实现 D触发器 -FPGA VERILOG D flip-flop