计数器 同步异步预置数清零 verilog hdl 编写-Asynchrony preset counter reset the Verilog HDL few prepared

采用verilog语言编写，实习双向计数器，并用四段数码管显示。包含四段数码管显示二进制数模块-Use verilog language internship bidirectional counter with four digital tube display. Contains four digital display binary number module

FPGA开发板做的一个简单LED驱动，使用Verilog语言实现- This is an example of a simple 32 bit up-counter called simple_counter.v It has a single clock input and a 32-bit output port module simple_count(input clock , output end of module counter

这是计数器的波形仿真文件属于vreilog的时序仿真-this is a verilog waveform file of a counter