FIFO的verilog实现，内附testbench和文档说明-FIFO verilog achieve, enclosing testbench and documentation shows

初步掌握ModelSim的使用方法,了解TestBench的编写,Verilog HDL的层次设计方法/参数设置、参数传递方法.-Preliminary master the use of ModelSim understand TestBench preparation, Verilog HDL level design methods/parameters, parameter passing methods.

It is a Verilog code for SPI master. It includes source code and a testbench to test the functionality.-It is a Verilog code for SPI master. It includes source code and a testbench to test the functionality.