计数器 同步异步预置数清零 verilog hdl 编写-Asynchrony preset counter reset the Verilog HDL few prepared

采用verilog语言编写，实习双向计数器，并用四段数码管显示。包含四段数码管显示二进制数模块-Use verilog language internship bidirectional counter with four digital tube display. Contains four digital display binary number module

这是计数器的波形仿真文件属于vreilog的时序仿真-this is a verilog waveform file of a counter