搜索资源列表
verilog source
- verilog的源代码。给出来常用的一些例程，对于verilog的使用和学习都有很大的帮助作用。-Verilog source code. Out to some routines commonly used for the use and Verilog study has been very helpful.
CAN协议控制器的Verilog实现
- 基于FPGA的CAN总线控制器，VERILOGHDL源代码，Q2仿真实现。可用。-FPGA-based CAN Bus Controller, VERILOGHDL source code, Q2 Simulation. Available.
pcit32_verilog_lattice
- 本文件是pci的verilog源代码程序-pci the Verilog source code procedures
verilogpll
- 用verilog语言编写的全数字锁相环的源代码,基于fpga平台-using Verilog language prepared by the DPLL the source code, they simply based on the platform
fifo-ram
- 采用Verilog语言描述的FIFO和双端口RAM源代码。
hdb3
- hdb3的发送端源代码，采用verilog可综合格式书写。已经在多款fpga和cpld芯片成功综合实现。
AD7865test1
- verilog hdl写的利用fpga控制ad7865进行多路ad数据采集的程序源代码。
uart_rx
- actel A3P250 fpga用VERILOG HDL语言实现串口功能的源代码
发一个基于ModelSim仿真的Verilog源代码包
- 发一个基于ModelSim仿真的Verilog源代码包-made a ModelSim simulation based on the Verilog source code
XPS_EMC.rar
- Xilinx EDK中SOC使用外部存储器接口（EMC）的方法，并用ISP1581举例说明了如何与时分复用总线（8051单片机总线）设备进行连接，有Verilog源代码。,Xilinx EDK in SOC using external memory interface (EMC) methods, and examples of how ISP1581 with the TDM bus (8051 bus) devices to connect, there Verilog source co
seqdet
- 对串行输入的数据流进行检测的ＶＥＲＩＬＯＧ源代码-On the serial input data streams to detect the Verilog source code
calculator
- EDA设计源代码，verilog计算器设计-EDA design source code, verilog calculator design
traffic
- verilog语言编写的交通灯程序源代码-the Verilog language of traffic lights program source code
CLOCK_GENERATOR
- 一个verilog时钟发生器源代码，能够满足最小时间间隔0.1ns的时钟计时要求。-A clock generator verilog source code, to meet the minimum time interval of 0.1ns clock timing requirements.
spimaster
- SD卡读写源代码.用Verilog编写.很不错.值得借鉴.特别对SD卡开发的人员!--SD card reader-writer source code. Prepared to use Verilog. Is pretty good. Be used for reference. In particular, the development of personnel SD card!
sen_ADF4350
- ADI公司ADF4350频率源芯片的verilog程序源代码，之前做过一个项目中的一部分，现在把代码拿来与大家分享-ADI' s ADF4350 frequency source chip verilog source code, done before a project part, and now the code is used to share with everyone
Altera-LVDS_IP
- 自己总结的Altera_LVDS的IP核的设计及仿真分析，已在实际工程中应用到，并且带有源代码和仿真代码，总结的文档，非常有用。(My summary of the Altera_LVDS IP kernel design and simulation analysis, has been applied in practical engineering, and with source code and simulation code, summary of the document, ver
8点fft
- 用quartus软件、verilog语言编写的8点fft源代码，代码简单易懂，整个代码只用了一个乘法器和一个加法器
Cameralink通信协议Verilog源代码
- 基于verilog的cameralink源代码