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freq_divider7
- 本程序为七分频数字电路的实现，采用VHDL语言编程，采用常见的奇数次分频方法实现，进仿真证实可用。其他奇数次可以直接修改程序中相关参数值即可直接移植引用-This procedure is the seventh-frequency digital circuits implemented using VHDL language programming, using a common method to achieve the odd division into simulation confi
dpll
- 数字锁相环 dpll的 编译通过,使用verilog HDL语言对锁相环进行基于FPGA的全数字系统设计,以及对其性能进行分析和计算机仿真的具体方法-Digital phase-locked loop dpll compiler through the use of verilog HDL language on the phase-locked loop FPGA-based digital system design, as well as its performance analysis
Elevator_controller_based_on_74
- 基于74系列数字芯片的8层电梯控制器，Multisim13仿真-An 8- layer elevator controller based on 74 series digital circuit chip.
模电multisim仿真实例
- 模拟和数字电子线路的仿真，可应用与单片机外围电路的设计(The simulation of analog electronic circuit and its application in the design of peripheral circuit of single chip computer.)
电子时钟 PROTEUS仿真
- 纯数字电路（无单片机）搭建电子时钟 PROTEUS仿真