3x3中值滤波器的FPGA实现(VERILOG),3x3 median filter FPGA implementation (VERILOG)

本文件是　基于ＦＰＧＡ的数字电路滤波器设计-This document is based on the number of FPGA circuit filter design

应用不同的用户可选择回旋滤波器的图像处理部件。一套PC应用程序将图像档案下载到一个FPGA可访问的存储器阵列。处理过的图像显示在连接的VGA显示屏上。 -Users can choose to apply a different room of the image processing filter components. A set of PC applications will be image files downloaded to a FPGA can access the memory

纯方位目标跟踪的伪线性卡尔曼滤波器FPGA实现。-The pseudo linear Kalman filter bearings target tracking FPGA.