搜索资源列表
video_stream_scaler
- Verilog HDL实现双线性插值视频实时缩放，源码及说明文档-Verilog HDL bilinear interpolation real-time zoom, video source and documentation
zynq_base_trd_14_3
- xilinx的视频处理参考Verilog代码-Video Targeted Reference Design On Xilinx FPGA With Verilog
BT656
- BT656资料中文版，可用于视频编解码，支持verilog等工具使用-BT656 information Chinese version can be used for video encoding and decoding, and other tools used to support verilog
02_VGA_VIP_YCbCr422_RGB888
- 用Verilog语言实现的视频源YCbCr422转为RGB888的算法，只用三个时钟完成-Verilog language to achieve the video source YCbCr422 to RGB888 algorithm, using only three clock
DCT
- 用Verilog HDL编写的离散余弦变换，可用于视频图像压缩，并在modelsim SE6.0中仿真通过-Verilog HDL prepared with discrete cosine transform can be used for video image compression, and modelsim SE6.0 simulation through
7_to_1-LVDS-dispaly-from-FLASH
- 该代码是基于verilog 实现的代码，可以用于对接受1080P的LVDS视频数据并处理后显示到各种规格的LCD屏幕上，且支持从FLASH中读取BMP的图片数据并实时显示到LCS屏幕-The code is based on the code verilog achieve, it can be used for receiving LVDS 1080P video and data processing displayed on a variety of LCD screen, and sup