搜索资源列表
djpeg_vlsi
- jpeg解码电路，是verilog编写的，可以综合，很有实用价值。-jpeg decoder circuit, is prepared verilog, synthesis, very practical value.
H.264Decoder
- H.264解码器，用verilog写成，可以在FPGA上实现baseline的264解码-H.264 decoder, written with verilog, can be achieved in the FPGA on the baseline of 264 decoding
H264
- h.264(verilog HDL) 这是基于流水线结构的H.264解码器源码-h.264 (verilog HDL) which is based on the pipeline structure of the H.264 decoder source code
dvi-code-verilog
- dvi encoder and decoder for fpga