3x3中值滤波器的FPGA实现(VERILOG),3x3 median filter FPGA implementation (VERILOG)

一个经过处理的FIR filter, verilog HDL实现在FPGA上-One new design of digital FIR filter , which can be implemented in FPGA kit

图像去噪算法的硬件实现，很完整，verilog语言编写的中值滤波，按模块编写，有3乘3模块，计算模块，计数模块-Hardware implementation of image denoising algorithm is very complete, verilog language median filter, according to the module to write, there are three by three module, calculation module, coun

图像处理的中值滤波器，使用verilog开发环境编程实现。-Verilog development environment programming median filter

完成滤波功能, 可以编译,转化为verlog代码.(This code complete filter funciton. It can be used and turned to Verilog code)