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sel_key
- verilog写的自动识别的加减计数器，挺好的，也算有自适应能力-Automatic Identification verilog written addition and subtraction counter, very good, and it has adaptive ability to count
VHDL
- odule vga_timing ( input wire clk_i, //输入时钟 40MHz input wire reset_i, //输入复位信号 output wire vga_pixel_flag, //输出像素有效 output reg vga_line_o, //输出水平信号 output reg vga_field_o, //输出垂直信号 output reg vga_frame_o //输出帧开始信号 ) //////////
CNT4
- 4位二进制加法计数器,每进入一个时钟脉冲，输出数就加1，从0000到1111循环输出计数-4-bit binary up counter,Each into a clock pulse output number is incremented from the 0000-1111 cycle of the output count
8sfdsd
- 用VHDL实现的八位可逆计数器，可作为交流学习使用。-VHDL implementation with eight reversible counter can be used as the exchange of learning to use.
shiyan6
- 实验六一位十进制计数器共阳极数码管，用共阳极管设计一个计数器-Experiment 6 One decimal digit counter common anode LED, common anode tube design with a counter