搜索资源列表
fft
- This example describes a 32K-point fast Fourier transform (FFT) using the Altera FFT IP MegaCore.
DPD_sim
- Digital Predistortion of Nonlieaner RF Power Amplifier with Memory Effects. This M code simulates a DPD technique linearization for a AB-class nonlinear HPA with memory effects. Here we consider a memory polynomial predistorter to modeling nonline
altera_cic_compensate_ip
- 级联积分梳妆滤波器的补偿滤波器，altera公司IP-altera cic compensate filter
USB1C6
- 基于ALTERA CYCLONE 系列的一个USB实验例程-ALTERA CYCLONE series based on a USB experimental routines
EXPT10_2_TENNIS
- 基于ALTERA CYCLONE 系列的乒乓球游戏实验例程-ALTERA CYCLONE series based on Games Table Tennis experimental routines
Music1
- 基于ALTERA CYCLONE 系列的音乐播放示例实验教程.-ALTERA CYCLONE series based on the music player tutorial sample experiment.
FIR3
- 3阶FIR，输入位宽12BIT ALTERA MAXPLUS II 及更高版本可打开-FIR
altera_mif_gen
- - mif generator on Altera using matlab
AN97011
- SAA7111和SAA7121的寄存器初始化官方配置，经过工程的考验-SAA7111 and SAA7121 official configuration register initialization, after the test engineering
gen_mif_1000
- 产生1000点正弦波、三角波、锯齿波的ALTERA MIF文件的源程序，可改为任意点.-1,000 points generated sine wave, triangle wave, sawtooth wave of ALTERA MIF file source, can be changed at any point.
nlpf
- This simple Matlab function simulates a innovative algorithm for narrow band interference mitigation for wireless communications, esp for satellite comm. The algorithm looks similar to LMS, but error is non-linearly transformed. It works well and a
ug_fft_2011
- ALtera 公司 QuartusII 软件中FFT Megacore 用户手册，2011年最新官方版！-ALtera company QuartusII software FFT Megacore user manual, 2011, the latest official version!
audio_patch_0p1
- audio patch sdi altera release
driver
- nios黑金源代码，altera sopc 工程文件，各个模块驱动代码-nios code
Clock-Divider
- this verilog program, Clock Divider, can be compiled successfully by Altera and ModelSIM.
impo_these_FPGA_SAPTONO_DEBYO_00_00
- this document is a thesis discuss about fpga implementation of signal processing system on targets such as altera and xilinx
MATLAB-and-Verilog-codes
- there are 5 files. the first two codes are written in Matlab as m-files in control system design to show step responses. in contrast, the final three codes are written in verilog ( Quartus II) used in Altera one of them for BCD adder and the other fo
比较全的ALTERA芯片的原理图和封装库
- 比较全的ALTERA芯片的原理图和封装库(Comparison of the ALTERA chip schematic and package library)