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canbus(FPGA)
- 基于FPGA的can 总线设计,采用verilog语言编写。在FPGA的开发环境下,新建一个工程,然后将本文件中的各个源代码添加进工程里,即可运行仿真。-FPGA-based bus design can use verilog language. FPGA development environment, a new project, and then the paper all the source code to add the project, Simulation can be run
LIP6492CORE_zigzag
- Compression ZingZang RTL Verilog source code
JPEG_Encoder_Verilog_Code
- 完整的JPEG解压缩代码,使用verilog编写的源程序-Complete JPEG decompression code,Prepared using verilog source
verilog1024fft
- 1024点FFT的verilog语言实现的源程序的代码-1024 fft verilog language workout source program code