The basic parts of the BFSK transmitter are the preamble and the data input circuit. The preamble sequence is positioned in front of each packet of 122 bits for a total of 128 bits packet. The main purpose of the preamble is to facilitate the recepti

产生（2，1，8）卷积码 ，其生成多项式为（561，753），二进制形式为（101110001，111101011）-Have (2,1,8) convolutional code, the generation polynomial for the (561,753), the binary form (101110001,111101011)

基于IEEE802.11n标准,采用verilog语言设计的(2,1,7)卷积码viterbi译码器,支持1/2,2/3,3/4,5/6四种码率的译码,以测试无误-IEEE802.11n standard Verilog language design (2,1,7) convolutional code viterbi decoder support 1/2, 2/3, 3/4, 5/6 four bit rate decoding to test and correct

(2,1,7)卷积码编码器 能设置初始状态和生成多项式的系数-(2,1,7) convolutional code encoder can set the initial state and the generator polynomial coefficients

采用（2,1,8）卷积码编码，采用viterbi译码算法进行解码(2,1,8 convolutional code is used, and Viterbi decoding algorithm is used to decode)