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vhdl
- 由两个与门和一个或非门构成的电路,其中A、B、C、D是输入,F是输出。-Two AND gates and a NOR gate circuit constituted, in which A, B, C, D is the input, F is the output.
lab-assignment1
- 这个是计算机结构的实验内容,主要包括逻辑门的设计(例如:与门,或门,非门).此外还有testbench的设计代码.-This is a computer architecture in experiments, including the design of logic gates (for example: AND gates, OR gates, NAND gate). Addition testbench design code.