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十进制计数器和数字钟
- 此程序是两个简单十进制计数器和数字钟，不完备之处请指教，谢谢！-this procedure is a simple two decimal counter and digital clock, from incomplete please enlighten, thank you!
cnt10
- 用VHDL语言编的带有异步清零功能的十进制计数器-using VHDL addendum to the asynchronous reset function with the decimal counter
8weishijinzhijishuqi
- 一个简单的8位十进制计数器源代码，VHDL实现编程-A simple 8-bit decimal counter source code, VHDL realization of programming
cntm9999
- 一个至少4位的十进制计数器，具有加减计数功能和置数功能，并能通过数码管显示计数结果。减数为零时发声报警。-At least four decimal counter with addition and subtraction functions and buy a few counting function, and can count the results of digital tube display. Decreases to zero when the audible alarm.
timer
- 一个有计数器功能的数字钟，两位数，十进制-a timer
10-couter
- 十进制计数器，需要在dos环境下运行，大学时写的程序-Decimal counter, you need to run in the dos environment, college writing program
design-a-decade-counter
- 设计一个四位二进制计数器，将计数结果由数码管显示，显示结果为十进制数。数码管选通为低电平有效，段码为高电平有效。-The design of a four-bit binary counter will count digital display, and displays the results as a decimal number. Digital tube strobe active-low segment code for active high.
VHDL
- 74LS161 JK触发器带清0端,项目名称为dff_JK_111 十进制计数器74LS290,项目名定为CTLS290：运算方法编写的290计数器：另一种编法LS290 不带使能端的3线8线译码器 八选一数具选择器：用CASE语句 全加器： 简单的JK触发器-74LS161 JK flip-flop with cleared end Project Name dff_JK_111 decade counter 74LS290 project name as CTLS290: and comp
VHDL_CNT10
- 带有异步复位和同步时钟使能的十进制加法计数器设计-With asynchronous reset and synchronous clock enable decimal addition counter design
LIBRARY-IEEE
- 六十进制BCD码计数器的源程序,将满60s产生的进位信号选送到分计数器。-sixty source of BCD decimal,carry signal will be generated by the 60s sent to counter